diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-03-08 14:04:52 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-09 21:40:09 +0000 |
| commit | d83faceefa77e9a769a7e6de4ad5313d5afc422a (patch) | |
| tree | 781336a2c4703b6e8c24910639ceb94685d88898 /src/soc/intel/common/block/lpc | |
| parent | 80edc84687e3babd5ce429c348eb5b55688dbad6 (diff) | |
soc/intel/common: Enable decoding of the COMB range to LPC based on Kconfig
By default all Intel platform has enable IO decode range for COMA if
CONFIG_DRIVERS_UART_8250IO is selected.
With this patch, COMB will get enable based on
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection.
Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid
an additional pci configuration read to get the same data.
Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/lpc')
| -rw-r--r-- | src/soc/intel/common/block/lpc/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpc/lpc_lib.c | 27 |
2 files changed, 25 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index c384c343f3..41e72c474a 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -3,3 +3,11 @@ config SOC_INTEL_COMMON_BLOCK_LPC help Use common LPC code for platform. Only soc specific code needs to be implemented as per requirement. + +config SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + depends on SOC_INTEL_COMMON_BLOCK_LPC && DRIVERS_UART_8250IO + bool + default n + help + By default COMA range to LPC is enable. COMB range to LPC is optional + and should select based on platform dedicated selection. diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index b4b3d1bb52..aeac441c23 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2018 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -25,13 +25,15 @@ #include "lpc_def.h" #include <soc/pci_devs.h> -void lpc_enable_fixed_io_ranges(uint16_t io_enables) +uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) { uint16_t reg_io_enables; reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); + + return io_enables; } /* @@ -225,15 +227,20 @@ void lpc_set_serirq_mode(enum serirq_mode mode) void lpc_io_setup_comm_a_b(void) { - /* - * Setup I/O Decode Range Register for LPC - * ComA Range 3F8h-3FFh [2:0] - * ComB Range 2F8h-2FFh [6:4] - */ - pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, - LPC_IOD_COMA_RANGE | LPC_IOD_COMB_RANGE); + /* ComA Range 3F8h-3FFh [2:0] */ + uint16_t com_ranges = LPC_IOD_COMA_RANGE; + uint16_t com_enable = LPC_IOE_COMA_EN; + + /* ComB Range 2F8h-2FFh [6:4] */ + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) { + com_ranges |= LPC_IOD_COMB_RANGE; + com_enable |= LPC_IOE_COMB_EN; + } + + /* Setup I/O Decode Range Register for LPC */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges); /* Enable ComA and ComB Port */ - lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN); + lpc_enable_fixed_io_ranges(com_enable); } static void lpc_set_gen_decode_range( |