soc/intel/common/pcie: Add helper function for getting mask of enabled ports

This change adds a helper function `pcie_rp_enable_mask()` that
returns a 32-bit mask indicating the status (enabled/disabled) of PCIe
root ports (in the groups table) as configured by the mainboard in the
device tree.

With this helper function, SoC chip config does not need to add
another `PcieRpEnable[]` config to identify what root ports are
enabled.

Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 15 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index ca50b13247..264c43f585 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -3,6 +3,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 
+#include <stdint.h>
+
 /*
  * The PCIe Root Ports usually come in groups of up to 8 PCI-device
  * functions.
@@ -34,4 +36,17 @@ struct pcie_rp_group {
  */
 void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
 
+/*
+ * Return mask of PCIe root ports that are enabled by mainboard. Mask is set in the same order
+ * as the root ports in pcie_rp_group groups table.
+ *
+ * Thus, the status of first root port in the groups table is indicated by bit 0 in the returned
+ * mask, second root port by bit 1 and so on.
+
+ * 1 in the bit position indicates root port is enabled, whereas 0 indicates root port is
+ * disabled. This function assumes that the maximum count of root ports in the groups table is
+ * <= 32.
+ */
+uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
+
 #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */