diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-01 08:47:51 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:06:53 +0000 |
| commit | 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch) | |
| tree | 8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/soc/intel/common/block/include | |
| parent | 603963e1ba4147ef31a72b94304708ab416e3b6a (diff) | |
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 154f03b81e..63b92013a3 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,13 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_ENABLE_VMX (1 << 2) -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ @@ -46,16 +39,13 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) -#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define MSR_IA32_PERF_CTL 0x199 -#define IA32_MISC_ENABLE 0x1a0 -/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 @@ -76,8 +66,6 @@ #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) #define MSR_PKG_POWER_SKU_UNIT 0x606 @@ -122,11 +110,6 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define MSR_IA32_PQR_ASSOC 0x0c8f -/* MSR bits 33:32 encode slot number 0-3 */ -#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) -#define MSR_IA32_L3_MASK_1 0x0c91 -#define MSR_IA32_L3_MASK_2 0x0c92 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ |