diff options
author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-09-07 12:15:45 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-11 21:26:27 +0000 |
commit | b051a9f5348abab842748577eaf4f06418df0ba3 (patch) | |
tree | 139e0c4938baa9b998c107642a45e78c613442b1 /src/soc/intel/common/block/include | |
parent | bfabe62a6e5cdd9e29394b12737c5ed9bd080036 (diff) |
soc/intel/skylake: Fix SPI WP disable status check
Use SPI write protect disable bit from BIOS_CONTROL register
to check write protect status.
Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21449
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/fast_spi.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 086143bc5f..6499ca5f5c 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -74,11 +74,18 @@ void fast_spi_cache_bios_region(void); * Caching. */ void fast_spi_early_init(uintptr_t spi_base_address); - /* * Fast SPI flash controller structure to allow SoCs to define bus-controller * mapping. */ extern const struct spi_ctrlr fast_spi_flash_ctrlr; +/* + * Read SPI Write protect disable bit. + */ +bool fast_spi_wpd_status(void); +/* + * Enable SPI Write protect. + */ +void fast_spi_enable_wp(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ |