diff options
author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-02-12 12:24:25 +0100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-02-20 23:17:39 +0000 |
commit | 5268b76801280667d8c27619fe2d771569c4e346 (patch) | |
tree | 075fa6b949b6719450755cdcdec912936a6754c2 /src/soc/intel/common/block/include | |
parent | e33f120cb808b946f3052019c9e4cf54b086491a (diff) |
src/soc: Fix various typos
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
4 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 73a9c9c6cd..927da3c214 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -44,7 +44,7 @@ unsigned long southbridge_write_acpi_tables(device_t device, struct acpi_rsdp *rsdp); /* - * Craetes acpi gnvs and adds it to the DSDT table. + * Creates acpi gnvs and adds it to the DSDT table. * GNVS creation is chipset specific and is done in soc specific acpi.c file. */ void southbridge_inject_dsdt(device_t device); @@ -84,7 +84,7 @@ void generate_t_state_entries(int core, int cores_per_package); /* * soc specific power states generation. We need this to be defined by soc * as the state generations varies in chipsets e.g. APL generates T and P - * states while SKL generates * P state only depening on a devicetree config + * states while SKL generates * P state only depending on a devicetree config */ void soc_power_states_generation(int core_id, int cores_per_package); diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 554c75d509..7269bef667 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -69,14 +69,14 @@ void lpc_close_pmio_windows(void); void lpc_open_mmio_window(uintptr_t base, size_t size); /* Returns true if given window is decoded to LPC via a fixed range. */ bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size); -/* Init SoC Spcific LPC features. Common definition will be weak and +/* Init SoC Specific LPC features. Common definition will be weak and each soc will need to define the init. */ void lpc_soc_init(struct device *dev); /* Fill up LPC IO resource structure inside SoC directory */ void pch_lpc_soc_fill_io_resources(struct device *dev); /* Init LPC GPIO pads */ void lpc_configure_pads(void); -/* Get SoC speicific MMIO ranges */ +/* Get SoC specific MMIO ranges */ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void); /* Set LPC BIOS Control BILD bit. */ void lpc_set_bios_interface_lock_down(void); @@ -97,7 +97,7 @@ void lpc_enable_pci_clk_cntl(void); void lpc_io_setup_comm_a_b(void); /* Enable PCH LPC by setting up generic decode range registers. */ void pch_enable_lpc(void); -/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */ +/* Retrieve and setup SoC specific PCH LPC interrupt routing. */ void soc_pch_pirq_init(const struct device *dev); /* Get SoC's generic IO decoder range register settings. */ void soc_get_gen_io_dec_range(const struct device *dev, diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 3827cf511a..d631f01d28 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -37,7 +37,7 @@ uint32_t soc_get_smi_status(uint32_t generic_sts); /* * This function is specific to soc and is defined as weak in common * pmclib file. SOC code can implement it for any special condition - * specific to the soc e.g. in SKL in handles deep S3 scenerio. + * specific to the soc e.g. in SKL in handles deep S3 scenario. * Return ACPI_SX values to indicate the previous sleep state. */ int soc_prev_sleep_state(const struct chipset_power_state *ps, @@ -206,7 +206,7 @@ const char * const *soc_std_gpe_sts_array(size_t *a); void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2); /* - * Reads soc specific power management crtitical registers, fills + * Reads soc specific power management critical registers, fills * chipset_power_state structure variable and prints. */ void soc_fill_power_state(struct chipset_power_state *ps); diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 64b2c36f05..a731b9cb0b 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -52,10 +52,10 @@ struct sa_mmio_descriptor { const char *description; }; -/* API to set Fixed MMIO addresss into PCI configuration space */ +/* API to set Fixed MMIO address into PCI configuration space */ void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources, size_t count); -/* API to set Fixed MMIO addresss into MCH base address */ +/* API to set Fixed MMIO address into MCH base address */ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources, size_t count); /* @@ -69,7 +69,7 @@ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt, * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h */ void enable_bios_reset_cpl(void); -/* API to enable PAM regisers */ +/* API to enable PAM registers */ void enable_pam_region(void); /* API to enable Power Aware Interrupt Routing through MCHBAR */ void enable_power_aware_intr(void); |