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authorV Sowmya <v.sowmya@intel.com>2020-11-11 07:04:13 +0530
committerFurquan Shaikh <furquan@google.com>2020-11-18 01:26:23 +0000
commit338b83c7b840198b537427ade46c54d7ddb217b1 (patch)
treed791125c9242b0b2b178d1e1774bbc1b19b3497a /src/soc/intel/common/block/include
parentf99055266bf2dba0cd85ade3bb0ba3ddeec5f7c7 (diff)
soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/B
In the existing implementation CSE RW metadata file is generated by scripts and to avoid incompitable issues between coreboot and the scripts this patch adds the follwing changes, * Move the metadata generation to the coreboot Makefile. * Add CBFS component type struct to create a metadata file during the compile time. * Extract the CSE RW version from SOC_INTEL_CSE_RW_VERSION config and update the major, minor, hotfix and build versions using the compile time flags. * Compute the hash of CSE RW binary in hex format using the openssl and use the HASH_BYTEARRAY macro to convert the 64 character hex values into the array. * Add the me_rw.metadata cbfs file to FW_MAIN_A and FW_MAIN_B regions. BUG=b:169077783 TEST= Built for dedede. Verify that metadata file was generated and added to the FW_MAIN_A/B. Extracted it using cbfstool and verfied that metadata was generated properly. Change-Id: I412581400a9606fa17cf4398faffda923f07b320 Signed-off-by: V Sowmya <v.sowmya@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cse.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index f554933ef4..64ee0ddd06 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -4,6 +4,7 @@
#define SOC_INTEL_COMMON_CSE_H
#include <types.h>
+#include <vb2_api.h>
/* MKHI Command groups */
#define MKHI_GROUP_ID_CBM 0x0
@@ -61,6 +62,24 @@ struct mkhi_hdr {
uint8_t result;
} __packed;
+/* CSE FW Version */
+struct fw_version {
+ uint16_t major;
+ uint16_t minor;
+ uint16_t hotfix;
+ uint16_t build;
+} __packed;
+
+/*
+ * CSE RW metadata structure
+ * fw_version - CSE RW firmware version
+ * sha256 - Hash of the CSE RW binary.
+ */
+struct cse_rw_metadata {
+ struct fw_version version;
+ uint8_t sha256[VB2_SHA256_DIGEST_SIZE];
+};
+
/* set up device for use in early boot enviroument with temp bar */
void heci_init(uintptr_t bar);
/*