diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-23 15:53:28 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-04 00:10:24 +0000 |
| commit | 14512f9a9be08d945830ddb6d0e48f4d6fc1635c (patch) | |
| tree | c8956704656524dd17be720079b8304149dd1620 /src/soc/intel/common/block/include | |
| parent | c3ab442cc1e1b36ae647eed6158ad10c9c93d3e6 (diff) | |
soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI
button and NMI functionality that can be triggered via IPMI. The purpose
of this is to cause the OS to create a system crashdump from a hang
system or for debugging.
Add code for enabling NMI interrupts on GPIOs configured with
PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI
function was copied and adapted. The `pad_community` struct gained two
variables for the registers.
Also register the NMI for LINT1 in the MADT in accordance to ACPI spec.
Test: Linux detects the NMI correctly in dmesg:
[ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/include')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 6e2bf1c138..173a383f1e 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -111,6 +111,8 @@ struct pad_community { uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */ uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */ uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */ + uint16_t gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */ + uint16_t gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */ uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */ uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ |