diff options
author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-09-23 20:59:38 +0530 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-09 19:19:46 +0000 |
commit | 8e4654527ef5fec658ca5aacad0612653d3dcf30 (patch) | |
tree | 5cf7d9519334074506d31e0e3fbc446457fe4463 /src/soc/intel/common/block/include | |
parent | 6d5f007813f6a2ffbdd6a633f31d207672eee2e1 (diff) |
soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC
Below changes are implemented:
1. Move HFSTS1 register definition to SoC since HFSTS1 register definition
is specific to a SoC. Moving structure back to SoC specific to avoid
unnecessay SoC specific macros in the common code.
2. Define a set of APIs in common code since CSE operation modes and
working states are same across SoCs.
cse_is_hfs1_com_normal(void)
cse_is_hfs1_com_secover_mei_msg(void)
cse_is_hfs1_com_soft_temp_disable(void)
cse_is_hfs1_cws_normal(void)
3. Modify existing code to use callbacks to get data of me_hfs1 structure.
TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards.
Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include')
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 515f1a47d5..46730707c8 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -51,30 +51,6 @@ enum { PCI_ME_HFSTS6 = 0x6C, }; -/* ME Host Firmware Status register 1 */ -union me_hfsts1 { - u32 data; - struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 reserved1: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 d3_support_valid: 1; - u32 d0i3_support_valid: 1; - } __packed fields; -}; - /* HECI Message Header */ struct mkhi_hdr { uint8_t group_id; @@ -172,4 +148,28 @@ int send_hmrfpo_get_status_msg(void); #define MKHI_HMRFPO_LOCKED 1 #define MKHI_HMRFPO_ENABLED 2 +/* + * Checks current working operation state is normal or not. + * Returns true if CSE's current working state is normal, otherwise false. + */ +bool cse_is_hfs1_cws_normal(void); + +/* + * Checks CSE's current operation mode is normal or not. + * Returns true if CSE's current operation mode is normal, otherwise false. + */ +bool cse_is_hfs1_com_normal(void); + +/* + * Checks CSE's current operation mode is SECOVER_MEI_MSG or not. + * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false. + */ +bool cse_is_hfs1_com_secover_mei_msg(void); + +/* + * Checks CSE's current operation mode is Soft Disable Mode or not. + * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false. + */ +bool cse_is_hfs1_com_soft_temp_disable(void); + #endif // SOC_INTEL_COMMON_CSE_H |