common/block/imc: Add Integrated Memory Controller (IMC) driver

IMC is found on certain Xeon processors. On such platforms SPDs are not
connected to SMBus on PCH but to dedicated IMC-owned pins. The purpose
of this driver is to expose access to the i2c/smbus controller associated
with IMC.

Datasheet used: Intel Xeon Processor D-1500 Product Family, Volume 2,
reference 332051-001

This driver is largely based on i2c-imc.c Linux driver.
https://lwn.net/Articles/685475/

TEST=single/double reads and single writes on Xeon-D1500.
Hardware: Open Compute Project Monolake platform.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Idbcda1c2273b9a5721fcd9470b4de182192779e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34678
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 38 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/imc.h b/src/soc/intel/common/block/include/intelblocks/imc.h
new file mode 100644
index 0000000000..fc3c241564
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/imc.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci.h>
+#include <stdint.h>
+
+#ifndef SOC_INTEL_COMMON_BLOCK_IMC_H
+#define SOC_INTEL_COMMON_BLOCK_IMC_H
+
+enum smbus_command { IMC_READ, IMC_WRITE };
+
+enum access_width { IMC_DATA_BYTE, IMC_DATA_WORD };
+
+enum memory_controller_id { IMC_CONTROLLER_ID0 = 0, IMC_CONTROLLER_ID1 };
+
+enum device_type_id {
+	IMC_DEVICE_TSOD = 0x3,
+	IMC_DEVICE_WP_EEPROM = 0x6,
+	IMC_DEVICE_EEPROM = 0xa
+};
+
+/* Initiate SMBus/I2C transaction to DIMM EEPROM */
+int imc_smbus_spd_xfer(pci_devfn_t dev, uint8_t slave_addr, uint8_t bus_addr,
+		       enum device_type_id dti, enum access_width width,
+		       enum memory_controller_id mcid, enum smbus_command cmd, void *data);
+#endif