diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-07 15:32:39 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:09:25 +0000 |
| commit | 4fafd412090d7de9a2ec6232ed22bbb1b1ce5dde (patch) | |
| tree | a6977fc548a989831a58ae21cc733ced126e629a /src/soc/intel/common/block/include/intelblocks | |
| parent | 5f52c0e91fc4ea545b6920157af7508b4a69a718 (diff) | |
soc/intel/common: add processor power limits control support
Add processor power limits control support under common code.
BRANCH=None
BUG=None
TEST=Built and checked this entry on Volteer system,
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/*
Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/power_limit.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h new file mode 100644 index 0000000000..2fa25de5be --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ +#define _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ + +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_PL3_CONTROL 0x615 +#define MSR_PLATFORM_POWER_LIMIT 0x65c + +/* Default power limit value in secs */ +#define MOBILE_SKU_PL1_TIME_SEC 28 + +struct soc_power_limits_config { + /* PL1 Override value in Watts */ + uint16_t tdp_pl1_override; + /* PL2 Override value in Watts */ + uint16_t tdp_pl2_override; + /* SysPL2 Value in Watts */ + uint16_t tdp_psyspl2; + /* SysPL3 Value in Watts */ + uint16_t tdp_psyspl3; + /* SysPL3 window size */ + uint32_t tdp_psyspl3_time; + /* SysPL3 duty cycle */ + uint32_t tdp_psyspl3_dutycycle; + /* PL4 Value in Watts */ + uint16_t tdp_pl4; + /* Estimated maximum platform power in Watts */ + uint16_t psys_pmax; +}; + +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time, + struct soc_power_limits_config *config); + +#endif /* _SOC_INTEL_COMMON_BLOCK_POWER_LIMIT_H_ */ |