intel/common/block/smm: Update smihandler to handle gpi

Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.

Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 18 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 4423904371..389d2415b8 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -109,6 +109,21 @@ void smihandler_southbridge_periodic(
 	const struct smm_save_state_ops *save_state_ops);
 
 /*
+ * This function should be implemented in SOC specific code to handle
+ * SMI GPIO_STS event. The default functionality is provided in
+ * soc/intel/common/block/smm/smihandler.c
+ */
+void smihandler_southbridge_gpi(
+	const struct smm_save_state_ops *save_state_ops);
+
+/*
+ * This function should be implemented in SOC specific code to handle
+ * SMI ESPI_STS event. The default functionality is provided in
+ * soc/intel/common/block/smm/smihandler.c
+ */
+void smihandler_southbridge_espi(
+	const struct smm_save_state_ops *save_state_ops);
+/*
  * This function returns a 1 or 0 depending on whether disable_busmaster
  * needs to be done for the specified device on S5 entry
  */
@@ -122,6 +137,9 @@ struct global_nvs_t *smm_get_gnvs(void);
 /* Mainboard handler for GPI SMIs */
 void mainboard_smi_gpi_handler(const struct gpi_status *sts);
 
+/* Mainboard handler for ESPI EMIs */
+void mainboard_smi_espi_handler(void);
+
 extern const struct smm_save_state_ops em64t100_smm_ops;
 
 extern const struct smm_save_state_ops em64t101_smm_ops;