diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-07 17:13:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-28 08:35:29 +0000 |
| commit | 7837c203d615fce03c6d89d99ba9a746619e49d4 (patch) | |
| tree | ba3626a10a35bd99108228611b18e7f76b7abd02 /src/soc/intel/common/block/include/intelblocks/p2sb.h | |
| parent | 210b351df3cc070f103feb01a40be9811af87906 (diff) | |
soc/intel/common/block: Move p2sb common functions into block/p2sb
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/p2sb.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/p2sb.h | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 8139a69b62..e5c1f3ef6a 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,37 @@ #ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H #define SOC_INTEL_COMMON_BLOCK_P2SB_H +#include <stddef.h> +#include <stdint.h> + +#define PCH_P2SB_E0 0xe0 +#define P2SB_E0_MASKLOCK (1 << 1) + +enum { + P2SB_EP_MASK_0_REG, + P2SB_EP_MASK_1_REG, + P2SB_EP_MASK_2_REG, + P2SB_EP_MASK_3_REG, + P2SB_EP_MASK_4_REG, + P2SB_EP_MASK_5_REG, + P2SB_EP_MASK_6_REG, + P2SB_EP_MASK_7_REG, + P2SB_EP_MASK_MAX_REG, +}; + void p2sb_unhide(void); void p2sb_hide(void); +void p2sb_disable_sideband_access(void); +void p2sb_enable_bar(void); +void p2sb_configure_hpet(void); + +/* SOC overrides */ +/* + * Each SoC should implement EP Mask register to disable SB access + * Input: + * ep_mask: An array to be filled by SoC code with EP mask register. + * count: number of element in EP mask array. + */ +void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count); #endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */ |