diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-02 08:44:47 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-05 01:38:15 +0000 |
| commit | 4e6b7907de07c9c7d4b01a6213a8e13e946398cb (patch) | |
| tree | d6cb8f208a588506710e36a38d141d9228af7483 /src/soc/intel/common/block/include/intelblocks/msr.h | |
| parent | 19c0ae540ea992b76eb65421381269def0a6328d (diff) | |
src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/msr.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431f3a..154f03b81e 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -25,14 +25,14 @@ #define SGX_GLOBAL_ENABLE (1 << 18) #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +/* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ #define CORE_C_STATE_LIMIT_C10_MASK 0x70 -/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +/* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ #define IO_MWAIT_REDIRECT_MASK 0x400 -/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +/* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ #define CST_CFG_LOCK_MASK 0x8000 #define MSR_BIOS_UPGD_TRIG 0x7a #define SGX_ACTIVATE_BIT (1) |