soc/intel/common: prepare for lpss clock split

Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.

BUG=b:75306520

Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
index c6caae2675..ca5568996f 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpss.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -22,8 +22,8 @@
 void lpss_reset_release(uintptr_t base);
 
 /*
- * Update clock divider parameters. Clock frequency is
- * configured as SOC_INTEL_COMMON_LPSS_CLOCK_MHZ * (M / N)
+ * Update clock divider parameters. Clock frequency is dependent on source
+ * clock frequency of each IP block. Resulting clock will be src_freq * (M / N).
  */
 void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);