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authorKarthikeyan Ramasubramanian <kramasub@chromium.org>2019-04-24 10:12:38 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-04-29 12:18:44 +0000
commit3391a31cf9e74fc9e40d876aa6689e98af38882d (patch)
treec2706780db612a6a714ead61dcb14e5a6e52001d /src/soc/intel/common/block/include/intelblocks/gpio.h
parentc126084bc53e0f74f6085f4f84b5bc387d701a4f (diff)
soc/intel/common: Add support to clear GPI IS & IE registers
Add support to reset the GPI Interrupt Status & Enable registers so that the system does not experience any interrupt storm from a GPI when it comes out of one of the sleep states. BUG=b:130593883 BRANCH=None TEST=Ensure that the Interrupt status & enable registers are reset during the boot up. Ensure that the system boots fine to ChromeOS. Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/gpio.h')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 147f6897a8..417929329f 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -209,5 +209,11 @@ uint8_t gpio_get_pad_portid(const gpio_t pad);
uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
int dw_reg, uint32_t reg_val);
+/*
+ * Function to reset/clear the GPI Interrupt Enable & Status registers for
+ * all GPIO pad communities.
+ */
+void gpi_clear_int_cfg(void);
+
#endif
#endif /* _SOC_INTELBLOCKS_GPIO_H_ */