diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-06-02 12:16:04 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-05 00:21:39 +0200 |
| commit | 5391e554e190d746ae54d09cd97c313736a04027 (patch) | |
| tree | 6e6df4ebbd466fbbdb12c2e4b64aa7d560a90be4 /src/soc/intel/common/block/include/intelblocks/fast_spi.h | |
| parent | d86e0e6638062b5d80f5d438f0741dd735734ad4 (diff) | |
soc/intel/common/block: add bios caching to fast spi module
Add fast_spi_cache_bios_region() that sets up a variable
MTRR as write-protect covering the fast spi BIOS region.
Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/fast_spi.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/fast_spi.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index e4bddc4e45..6294001d23 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -57,6 +57,10 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); */ size_t fast_spi_get_bios_region(size_t *bios_size); /* + * Cache the memory-mapped BIOS region as write-protect type. + */ +void fast_spi_cache_bios_region(void); +/* * Program temporary BAR for FAST_SPI in case any of the stages before ramstage * need to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI * enumeration. Also, Disable the BIOS write protect and Enable Prefetching and |