diff options
author | Chris Ching <chingcodes@chromium.org> | 2017-12-06 14:26:15 -0700 |
---|---|---|
committer | Chris Ching <chingcodes@chromium.org> | 2017-12-22 16:39:42 +0000 |
commit | b8dc63bdfe04fc15553f1ea6e42583cbdaad38ac (patch) | |
tree | 6c25cdb3bb62df3cb80b01f111467b98800d18d0 /src/soc/intel/common/block/i2c/lpss_i2c.h | |
parent | 17e85adc91d905919f8c4a512125ebd457ce99db (diff) |
ic2/designware: Move Intel i2c logic to shared driver
BUG=b:70232394
BRANCH=none
TEST=emerge-reef coreboot
emerge-glados
Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/i2c/lpss_i2c.h')
-rw-r--r-- | src/soc/intel/common/block/i2c/lpss_i2c.h | 99 |
1 files changed, 0 insertions, 99 deletions
diff --git a/src/soc/intel/common/block/i2c/lpss_i2c.h b/src/soc/intel/common/block/i2c/lpss_i2c.h deleted file mode 100644 index 72341621c0..0000000000 --- a/src/soc/intel/common/block/i2c/lpss_i2c.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <compiler.h> -#include <intelblocks/lpss_i2c.h> - -#define LPSS_DEBUG BIOS_NEVER - -/* I2C Controller MMIO register space */ -struct lpss_i2c_regs { - uint32_t control; - uint32_t target_addr; - uint32_t slave_addr; - uint32_t master_addr; - uint32_t cmd_data; - uint32_t ss_scl_hcnt; - uint32_t ss_scl_lcnt; - uint32_t fs_scl_hcnt; - uint32_t fs_scl_lcnt; - uint32_t hs_scl_hcnt; - uint32_t hs_scl_lcnt; - uint32_t intr_stat; - uint32_t intr_mask; - uint32_t raw_intr_stat; - uint32_t rx_thresh; - uint32_t tx_thresh; - uint32_t clear_intr; - uint32_t clear_rx_under_intr; - uint32_t clear_rx_over_intr; - uint32_t clear_tx_over_intr; - uint32_t clear_rd_req_intr; - uint32_t clear_tx_abrt_intr; - uint32_t clear_rx_done_intr; - uint32_t clear_activity_intr; - uint32_t clear_stop_det_intr; - uint32_t clear_start_det_intr; - uint32_t clear_gen_call_intr; - uint32_t enable; - uint32_t status; - uint32_t tx_level; - uint32_t rx_level; - uint32_t sda_hold; - uint32_t tx_abort_source; - uint32_t slv_data_nak_only; - uint32_t dma_cr; - uint32_t dma_tdlr; - uint32_t dma_rdlr; - uint32_t sda_setup; - uint32_t ack_general_call; - uint32_t enable_status; - uint32_t fs_spklen; - uint32_t hs_spklen; - uint32_t clr_restart_det; - uint32_t comp_param1; - uint32_t comp_version; - uint32_t comp_type; -} __packed; - -/* Get I2C controller base address */ -uintptr_t lpss_i2c_base_address(unsigned int bus); - -/* - * Initialize this bus controller and set the speed - * Return value: - * -1 = failure - * 0 = success -*/ -int lpss_i2c_init(unsigned int bus, const struct lpss_i2c_bus_config *bcfg); - -/* - * Generate speed cofnig based on clock - * Return value: - * -1 = failure - * 0 = success -*/ -int lpss_i2c_gen_speed_config(struct lpss_i2c_regs *regs, - enum i2c_speed speed, - const struct lpss_i2c_bus_config *bcfg, - struct lpss_i2c_speed_config *config); - -/* - * Process given I2C segments in a single transfer - * Return value: - * -1 = failure - * 0 = success - */ -int lpss_i2c_transfer(unsigned int bus, const struct i2c_msg *, size_t count); |