diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-23 15:53:28 +0100 |
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committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-04 00:10:24 +0000 |
commit | 14512f9a9be08d945830ddb6d0e48f4d6fc1635c (patch) | |
tree | c8956704656524dd17be720079b8304149dd1620 /src/soc/intel/common/block/gpio | |
parent | c3ab442cc1e1b36ae647eed6158ad10c9c93d3e6 (diff) |
soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI
button and NMI functionality that can be triggered via IPMI. The purpose
of this is to cause the OS to create a system crashdump from a hang
system or for debugging.
Add code for enabling NMI interrupts on GPIOs configured with
PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI
function was copied and adapted. The `pad_community` struct gained two
variables for the registers.
Also register the NMI for LINT1 in the MADT in accordance to ACPI spec.
Test: Linux detects the NMI correctly in dmesg:
[ 0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/gpio')
-rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 0d21c8a8b6..fb9287c1f7 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -48,6 +48,10 @@ ((group) * sizeof(uint32_t))) #define GPI_SMI_EN_OFFSET(comm, group) ((comm)->gpi_smi_en_reg_0 + \ ((group) * sizeof(uint32_t))) +#define GPI_NMI_STS_OFFSET(comm, group) ((comm)->gpi_nmi_sts_reg_0 + \ + ((group) * sizeof(uint32_t))) +#define GPI_NMI_EN_OFFSET(comm, group) ((comm)->gpi_nmi_en_reg_0 + \ + ((group) * sizeof(uint32_t))) #define GPI_IS_OFFSET(comm, group) ((comm)->gpi_int_sts_reg_0 + \ ((group) * sizeof(uint32_t))) #define GPI_IE_OFFSET(comm, group) ((comm)->gpi_int_en_reg_0 + \ @@ -176,6 +180,35 @@ static void gpi_enable_smi(const struct pad_config *cfg, pcr_or32(comm->port, en_reg, en_value); } +static void gpi_enable_nmi(const struct pad_config *cfg, + const struct pad_community *comm) +{ + uint16_t sts_reg; + uint16_t en_reg; + uint32_t en_value; + int group; + int pin; + + if (((cfg->pad_config[0]) & PAD_CFG0_ROUTE_NMI) != PAD_CFG0_ROUTE_NMI) + return; + + /* Do not configure NMI if the platform doesn't support it */ + if (!comm->gpi_nmi_sts_reg_0 || !comm->gpi_nmi_en_reg_0) + return; + + pin = relative_pad_in_comm(comm, cfg->pad); + group = gpio_group_index(comm, pin); + sts_reg = GPI_NMI_STS_OFFSET(comm, group); + en_reg = GPI_NMI_EN_OFFSET(comm, group); + en_value = gpio_bitmask_within_group(comm, pin); + + /* Write back 1 to reset the sts bit */ + pcr_rmw32(comm->port, sts_reg, en_value, 0); + + /* Set enable bits */ + pcr_or32(comm->port, en_reg, en_value); +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -283,6 +316,7 @@ static void gpio_configure_pad(const struct pad_config *cfg) gpio_configure_itss(cfg, comm->port, config_offset); gpio_configure_owner(cfg, comm); gpi_enable_smi(cfg, comm); + gpi_enable_nmi(cfg, comm); } void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) |