soc/intel/common: Provide common block fast_spi_flash_ctrlr

Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.

Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 15 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
index 3babf914b7..27a4bb7886 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
@@ -350,3 +350,18 @@ int fast_spi_flash_read_wpsr(u8 *sr)
 
 	return 0;
 }
+
+static int fast_spi_flash_ctrlr_setup(const struct spi_slave *dev)
+{
+	if (dev->cs != 0) {
+		printk(BIOS_ERR, "%s: Invalid CS for fast SPI bus=0x%x,cs=0x%x!\n",
+		       __func__, dev->bus, dev->cs);
+		return -1;
+	}
+
+	return 0;
+}
+
+const struct spi_ctrlr fast_spi_flash_ctrlr = {
+	.setup = fast_spi_flash_ctrlr_setup,
+};