diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-08-17 11:49:27 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 18:06:25 +0000 |
| commit | 4f6e341e88e94e81087a1538b3364dcd47641c7f (patch) | |
| tree | 31f663abad816df9d4b7d9733d1773d34c78a35d /src/soc/intel/common/block/fast_spi/fast_spi_def.h | |
| parent | 639bf8a4bd977ec6b44ee008cadcffca85ae61e2 (diff) | |
soc/intel/common: Add function to DLOCK PR registers
Add a function in FAST_SPI library to discrete lock the PR
registers 0 to 4.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/fast_spi/fast_spi_def.h')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi_def.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 8e06df28de..a389e34154 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -34,6 +34,7 @@ #define SPIBAR_BFPREG 0x00 #define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_FADDR 0x08 +#define SPIBAR_DLOCK 0x0c #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) #define SPIBAR_FPR_BASE 0x84 #define SPIBAR_FPR(n) 0x84 + (4 * n)) @@ -87,6 +88,13 @@ /* Bit definitions for FADDR (0x08) register */ #define SPIBAR_FADDR_MASK 0x7FFFFFF +/* Bit definitions for DLOCK (0x0C) register */ +#define SPIBAR_DLOCK_PR0LOCKDN (1 << 8) +#define SPIBAR_DLOCK_PR1LOCKDN (1 << 9) +#define SPIBAR_DLOCK_PR2LOCKDN (1 << 10) +#define SPIBAR_DLOCK_PR3LOCKDN (1 << 11) +#define SPIBAR_DLOCK_PR4LOCKDN (1 << 12) + /* Maximum bytes of data that can fit in FDATAn (0x10) registers */ #define SPIBAR_FDATA_FIFO_SIZE 0x40 |