diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-02-16 17:22:37 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-01 16:26:26 +0200 |
| commit | 89331cd4c877397adf6b35002d864ac105dfc827 (patch) | |
| tree | bcef0ac94cb98df6a3ff127dd2fa2cdcfda2e6f5 /src/soc/intel/common/block/fast_spi/Kconfig | |
| parent | 281ccca373c3b7c96452f35815fcf11274678117 (diff) | |
soc/intel/common/block: Add Intel common FAST_SPI code
Create Intel Common FAST_SPI Controller code.
This code contains the code for SPI initialization which has
the following programming -
* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
* Implement FAST_SPI read, write, erase APIs.
Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/fast_spi/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig new file mode 100644 index 0000000000..87edb92095 --- /dev/null +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_FAST_SPI + bool + help + Intel Processor common FAST_SPI support |