diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-29 15:20:56 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-07-07 20:31:14 +0000 |
| commit | c5316ec4d675750f35ff1b383adacc2255e92d79 (patch) | |
| tree | 9def7221ee37b1c5939f7a9d35e8ba5f0c0fd942 /src/soc/intel/common/block/dtt/Kconfig | |
| parent | 3452cb1359229b0457e9e1f6282c67fd459d4c90 (diff) | |
soc/intel/common/block: Add new block DTT
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.
Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/dtt/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/dtt/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/dtt/Kconfig b/src/soc/intel/common/block/dtt/Kconfig new file mode 100644 index 0000000000..063c475d53 --- /dev/null +++ b/src/soc/intel/common/block/dtt/Kconfig @@ -0,0 +1,7 @@ +config SOC_INTEL_COMMON_BLOCK_DTT + bool + default n + help + Minimal PCI Driver for enabling SSDT generation of Intel + Dynamic Tuning Technology (DTT) policies and controls, also + known as Intel DPTF (Dynamic Platform and Thermal Framework) |