soc/intel/cpulib: Remove redundent enable/disable functions

This patch removes multiple enable/disable function definitions and
make use of single function with argument to know feature status
(enable/disable).

Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32282
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 16 insertions, 30 deletions

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 9964f2b02c..a7f89baafd 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -185,50 +185,36 @@ int cpu_get_burst_mode_state(void)
 }
 
 /*
- * Enable Burst mode.
+ * Program CPU Burst mode
+ * true = Enable Burst mode.
+ * false = Disable Burst mode.
  */
-void cpu_enable_burst_mode(void)
+void cpu_burst_mode(bool burst_mode_status)
 {
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.hi &= ~BURST_MODE_DISABLE;
+	if (burst_mode_status)
+		msr.hi &= ~BURST_MODE_DISABLE;
+	else
+		msr.hi |= BURST_MODE_DISABLE;
 	wrmsr(IA32_MISC_ENABLE, msr);
 }
 
 /*
- * Disable Burst mode.
+ * Program Enhanced Intel Speed Step Technology
+ * true = Enable EIST.
+ * false = Disable EIST.
  */
-void cpu_disable_burst_mode(void)
+void cpu_set_eist(bool eist_status)
 {
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.hi |= BURST_MODE_DISABLE;
-	wrmsr(IA32_MISC_ENABLE, msr);
-}
-
-/*
- * Enable Intel Enhanced Speed Step Technology.
- */
-void cpu_enable_eist(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
-	wrmsr(IA32_MISC_ENABLE, msr);
-}
-
-/*
- * Disable Intel Enhanced Speed Step Technology.
- */
-void cpu_disable_eist(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
+	if (eist_status)
+		msr.lo |= (1 << 16);
+	else
+		msr.lo &= ~(1 << 16);
 	wrmsr(IA32_MISC_ENABLE, msr);
 }