soc/intel/common: Add funtion to modify PAT & NXE bit

Add function to modify NXE bit & PAT.

BUG=None
BRANCH=None
TEST=Make sure build for Glkrvp is successful.

Change-Id: I265d6d5ca538496934a375eb8d99d52879522051
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25480
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 20 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 0d6dacc628..ed1ba0fa7b 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -314,3 +314,23 @@ void mca_configure(void)
 			(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
 	}
 }
+
+void set_nxe(uint8_t enable)
+{
+	msr_t msr = rdmsr(IA32_EFER);
+
+	if (enable)
+		msr.lo |= EFER_NXE;
+	else
+		msr.lo &= ~EFER_NXE;
+
+	wrmsr(IA32_EFER, msr);
+}
+
+void set_pat(uint64_t pat)
+{
+	msr_t msr;
+	msr.lo = pat;
+	msr.hi = pat >> 32;
+	wrmsr(MSR_IA32_PAT, msr);
+}