aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/common/block/cpu
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2020-07-22 11:44:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-26 21:35:12 +0000
commit23a60fa65bf2ef0e5a31b026830301d7ce0d10ab (patch)
tree7c0d7aaa3192f38be676a80938c0728cd4e4f01e /src/soc/intel/common/block/cpu
parenta83a7db80445469369c769ad252e245d0b8e484f (diff)
src/soc/intel: Add include <types.h>
BIT(x) needs <types.h>. Change-Id: I674e3e423e06ee869366ebbd7c9d4248a2f3d9d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/cpu')
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 0cebe329c0..5b703cfcb4 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -9,7 +9,7 @@
#include <intelblocks/fast_spi.h>
#include <intelblocks/msr.h>
#include <soc/soc_chip.h>
-#include <stdint.h>
+#include <types.h>
/*
* Set PERF_CTL MSR (0x199) P_Req with