diff options
| author | Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> | 2020-12-03 14:07:15 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-14 23:05:25 +0000 |
| commit | 87c7ec7c0677ec5fda4a9cebb95c06edb23a96ba (patch) | |
| tree | 0851933ccc52497f866c0aebaff15871db8375c6 /src/soc/intel/common/block/cpu/car | |
| parent | 5f7343273708490137163445c4a3ba38ed2b7b1e (diff) | |
soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cpu/car')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 97bffb0062..b60e797b2f 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -415,7 +415,7 @@ set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ mov %eax, %ebx /* back up the non-eviction mask */ /* - * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 + * Program MSR 0xC91 IA32_L3_MASK_1 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction @@ -428,26 +428,18 @@ set_eviction_mask: xor $~0, %eax /* invert 32 bits */ and %ecx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_1, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_1, %ecx -#endif xorl %edx, %edx wrmsr /* - * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2 + * Program MSR 0xC92 IA32_L3_MASK_2 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ mov %ebx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_2, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_2, %ecx -#endif xorl %edx, %edx wrmsr /* |