diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-07-16 09:03:06 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-14 07:02:26 +0000 |
| commit | c1d227d3120470a9e0b0d9d6f58d334782117820 (patch) | |
| tree | 6a9ccc01bd28988187346c64184468a36bc800bf /src/soc/intel/common/block/cpu/Kconfig | |
| parent | 1ba86f685b87c2467518eb04beaa36f16349570f (diff) | |
soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.
The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.
TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.
Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.
BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
CAR configuration.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/cpu/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/cpu/Kconfig | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b2401e..1351cb8e1d 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,6 +51,28 @@ config INTEL_CAR_NEM_ENHANCED ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config USE_CAR_NEM_ENHANCED_V1 + bool + select INTEL_CAR_NEM_ENHANCED + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + SKL, KBL, CNL, WHL, CML and ICL and JSL platforms. + +config USE_CAR_NEM_ENHANCED_V2 + bool + select INTEL_CAR_NEM_ENHANCED + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + TGL platform. + +config COS_MAPPED_TO_MSB + bool + depends on INTEL_CAR_NEM_ENHANCED + help + On TGL and JSL platform the class of service configuration + is mapped to MSB of MSR IA32_PQR_ASSOC. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n |