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authorFurquan Shaikh <furquan@google.com>2021-01-19 11:55:08 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-21 11:00:54 +0000
commit3b6b9c7b783f2005952c1521dba30fd5b598e68e (patch)
treee906f1994bd3ba084ae84a6579017bd8b024bd95 /src/soc/intel/common/basecode
parent985821c4f2feda41ed2d1ab83f6ae7b8f15197bd (diff)
soc/intel/common/pcie_rp.h: Fix comment style
This change updates pcie_rp.h to reflow the comment blocks to fit within 80 columns to match the original style of the file. This addresses comment received on CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/). Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/common/basecode')
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