diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-03-09 20:35:32 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-25 13:55:59 +0000 |
| commit | 0aa1ac41c33e6cd53c42c6b697b676c0f3ced3eb (patch) | |
| tree | 33536e8ebcad80d634cd8404342d2a811a3c65f2 /src/soc/intel/common/basecode | |
| parent | 574f3c8fe44593c9bba8e283f1e1f0b0cebea980 (diff) | |
soc/intel/common: Add support to control CSE firmware update
The patch adds support to control CSE Lite firmware update dynamically.
In order to disable the CSE firmware update functionality, offset 0xf00
in the coreboot binary be updated with 0x1.
Run below command on the binary to disable CSE firmwar update
printf '\x01' | dd of=image-brya4es.serial.bin bs=1 seek=3840 count=1
conv=notrunc
BUG=b:153410586
TEST=Verified CSE firmware update functionality is not getting
triggered after updating the offset:0xF00 in the coreboot binary.
........................ CB Logs ......................................
[DEBUG] prev_sleep_state 5
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
[DEBUG] cse_lite: Flags = 0x3
[DEBUG] cse_lite: RO version = 16.0.15.1752 (Status=0x0, Start=0x2000,
End=0x19bfff)
[DEBUG] cse_lite: RW version = 16.0.15.1752 (Status=0x0,
Start=0x205000, End=0x439fff)
rt_debug: pre_mem_debug.cse_fw_update_disable=1
[DEBUG] Boot Count incremented to 956
.......................................................................
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/common/basecode')
| -rw-r--r-- | src/soc/intel/common/basecode/debug/debug_feature.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h | 3 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/common/basecode/debug/debug_feature.c b/src/soc/intel/common/basecode/debug/debug_feature.c index 42cf992afa..1c55f0b887 100644 --- a/src/soc/intel/common/basecode/debug/debug_feature.c +++ b/src/soc/intel/common/basecode/debug/debug_feature.c @@ -10,7 +10,8 @@ #define SI_DESC_REGION_SZ 4096 struct pre_mem_ft { - uint8_t reserved[64]; + uint8_t cse_fw_update_disable; /* Byte location: 0xF00 */ + uint8_t reserved[63]; }; static struct pre_mem_ft pre_mem_debug; @@ -18,6 +19,14 @@ static struct pre_mem_ft pre_mem_debug; _Static_assert(sizeof(struct pre_mem_ft) % 64 == 0 && sizeof(struct pre_mem_ft) <= 256, "sizeof(struct pre_mem_ft) must be a multiple of 64 bytes and up to 256 bytes"); +bool is_debug_cse_fw_update_disable(void) +{ + printk(BIOS_DEBUG, "rt_debug: pre_mem_debug.cse_fw_update_disable=%d\n", + pre_mem_debug.cse_fw_update_disable); + + return pre_mem_debug.cse_fw_update_disable == 1; +} + uint8_t pre_mem_debug_init(void) { if (spi_flash_read(boot_device_spi_flash(), PRE_MEM_FEATURE_CTRL_OFFSET, diff --git a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h index fabf27ddd8..51e3f4d05a 100644 --- a/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h +++ b/src/soc/intel/common/basecode/include/intelbasecode/debug_feature.h @@ -5,6 +5,9 @@ #include <types.h> +/* Check if CSE firmware update is enabled or not */ +bool is_debug_cse_fw_update_disable(void); + /* * Reads OEM Section area in the Descriptor Region and * populates pre_mem_debug structure. |