diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-17 15:36:45 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-11-09 16:02:19 +0000 |
| commit | b48caadad54196245f0e7dfcb92caa21e7112307 (patch) | |
| tree | 7652c60718b3eac5f008fba0a8fee34511aa8560 /src/soc/intel/common/acpi | |
| parent | cc66b56c80862a59117a4582abc8d59f092ac59c (diff) | |
soc/intel: generate SSDT instead of using GNVS for SGX
GNVS should not be used for values that are static at runtime. Thus,
use SSDT for the SGX fields.
Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/common/acpi')
| -rw-r--r-- | src/soc/intel/common/acpi/sgx.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/acpi/sgx.asl b/src/soc/intel/common/acpi/sgx.asl index 9aea7a8b09..cfd7f7ed2a 100644 --- a/src/soc/intel/common/acpi/sgx.asl +++ b/src/soc/intel/common/acpi/sgx.asl @@ -6,6 +6,9 @@ Scope(\_SB) // Secure Enclave memory Device (EPC) { + External (EPCS, IntObj) + External (EMNA, IntObj) + External (ELNG, IntObj) Name (_HID, EISAID ("INT0E0C")) Name (_STR, Unicode ("Enclave Page Cache 1.0")) Name (_MLS, Package () { |