soc/intel/common/acpi: Support on/off PCIe CLK by P2SB

In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it
needs PMC IPC cmd to turn on/off the corresponding clock.

Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on
IOE or SoC die.

BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard pcie port doesn't block S0ix with RTD3 cold enabled.

Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 104 insertions, 0 deletions

diff --git a/src/soc/intel/common/acpi/ioe_clk.asl b/src/soc/intel/common/acpi/ioe_clk.asl
new file mode 100644
index 0000000000..9aa1aba4f5
--- /dev/null
+++ b/src/soc/intel/common/acpi/ioe_clk.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define PCR_BIOS_BUFFEN 0x8080
+
+Scope (\_SB)
+{
+	/* MTL IOE CLK */
+	Device (ECLK) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, "IOECLK")
+
+		Method (_STA)
+		{
+			/*
+			 * Device is present, enabled and decoding its resources
+			 * and should not be shown in UI
+			 */
+			Return (0x3)
+		}
+
+		/*
+		 * PCIe(100MHz) clock disable
+		 * Arg0 - clock index
+		 */
+		Method (CLKD, 1) {
+			\_SB.PCI0.ICRA (PID_ISCLK, PCR_BIOS_BUFFEN, Not (ShiftLeft (1, Arg0)))
+		}
+
+		/*
+		 * PCIe(100MHz) clock enable
+		 * Arg0 - clock index
+		 */
+		Method (CLKE, 1) {
+			\_SB.PCI0.ICRO (PID_ISCLK, PCR_BIOS_BUFFEN, (ShiftLeft (1, Arg0)))
+		}
+	}
+}
diff --git a/src/soc/intel/common/acpi/pch_clk.asl b/src/soc/intel/common/acpi/pch_clk.asl
new file mode 100644
index 0000000000..08863a3234
--- /dev/null
+++ b/src/soc/intel/common/acpi/pch_clk.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define PCR_BIOS_BUFFEN 0x8080
+
+Scope (\_SB)
+{
+	/* MTL PCH CLK */
+	Device (ICLK) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, "SOCCLK")
+
+		Method (_STA)
+		{
+			/*
+			 * Device is present, enabled and decoding its resources
+			 * and should not be shown in UI
+			 */
+			Return (0x3)
+		}
+
+		/*
+		 * PCIe(100MHz) clock disable
+		 * Arg0 - clock index
+		 */
+		Method (CLKD, 1) {
+			\_SB.PCI0.PCRA (PID_ISCLK, PCR_BIOS_BUFFEN, Not (ShiftLeft (1, Arg0)))
+		}
+
+		/*
+		 * PCIe(100MHz) clock enable
+		 * Arg0 - clock index
+		 */
+		Method (CLKE, 1) {
+			\_SB.PCI0.PCRO (PID_ISCLK, PCR_BIOS_BUFFEN, (ShiftLeft (1, Arg0)))
+		}
+	}
+}
diff --git a/src/soc/intel/common/acpi/pcie_clk.asl b/src/soc/intel/common/acpi/pcie_clk.asl
new file mode 100644
index 0000000000..e7e311fe9c
--- /dev/null
+++ b/src/soc/intel/common/acpi/pcie_clk.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* PCH clock by P2SB */
+#include <soc/intel/common/acpi/pch_clk.asl>
+
+/* IOE clock by P2SB */
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
+	#include <soc/intel/common/acpi/ioe_clk.asl>
+#endif
+
+/*
+ * Configure PCIe ClkReq Override
+ * Arg0: Clock number
+ * Arg1: Enable(1)/Disable(0) Clock
+ */
+Method (SPCO, 2, Serialized) {
+	If (LEqual (Arg1,1)) {
+		If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
+			\_SB.ECLK.CLKE (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
+		} Else {
+			\_SB.ICLK.CLKE (Arg0)
+		}
+	} Else {
+		If (LGreaterEqual (Arg0, CONFIG_IOE_DIE_CLOCK_START)) {
+			\_SB.ECLK.CLKD (Subtract (Arg0, CONFIG_IOE_DIE_CLOCK_START))
+		} Else {
+			\_SB.ICLK.CLKD (Arg0)
+		}
+	}
+}