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author | Duncan Laurie <dlaurie@chromium.org> | 2018-05-07 11:56:52 -0700 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2018-05-08 14:40:23 +0000 |
commit | 8735d1bdc7ff76ee643472012af026e92d82477a (patch) | |
tree | 8a390a43e9419badb06a136fc689bfcb35c33da5 /src/soc/intel/common/acpi | |
parent | 3e582d1613c9df08b0a0a745cd720bd397b0cf49 (diff) |
soc/intel/skylake: Support PCH UART 0 and 1 for console
The current PCH UART support for console is limited to UART2.
This change adds support for specifying UART0 or UART1 to be
used instead by changing CONFIG_UART_FOR_CONSOLE in the board
level Kconfig. The default is still 2.
This is tested with a board that uses UART0 for debug output.
Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/26140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/acpi')
0 files changed, 0 insertions, 0 deletions