diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-31 21:07:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 10:43:40 +0000 |
| commit | 2b2ade96384791d7320d87bc0e29445002b6d246 (patch) | |
| tree | fecae64abfc0d357d75fc62ccb9b9157e516bb9a /src/soc/intel/common/Makefile.inc | |
| parent | 22d4397913ca3a3b42ad24b44f20ee08bee19b22 (diff) | |
soc/intel/common: Create common Intel FSP reset code block
Create SOC_INTEL_COMMON_FSP_RESET Kconfig to have IA common code block
to handle platform reset request raised by FSP. The FSP will use the
FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset
is required.
Make FSP_STATUS_GLOBAL_RESET depends on SOC_INTEL_COMMON_FSP_RESET.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/Makefile.inc')
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 22d350ccdb..9993bceedf 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -27,6 +27,9 @@ romstage-$(CONFIG_TPM_CR50) += tpm_tis.c ramstage-$(CONFIG_TPM_CR50) += tpm_tis.c postcar-$(CONFIG_TPM_CR50) += tpm_tis.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RESET) += fsp_reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RESET) += fsp_reset.c + ifeq ($(CONFIG_MMA),y) MMA_BLOBS_PATH = $(call strip_quotes,$(CONFIG_MMA_BLOBS_PATH)) MMA_TEST_NAMES = $(notdir $(wildcard $(MMA_BLOBS_PATH)/tests/*)) |