diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 12:07:03 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:03 +0100 |
| commit | 94b856ef9afaca880909d22b24d5443408c47920 (patch) | |
| tree | 14a76715a13535b5c2991103adf4820f776f1dd5 /src/soc/intel/common/Makefile.inc | |
| parent | 597de2849d8a0861ba0d7fca32948bdf37378eed (diff) | |
FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values
associated with this common code.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/common/Makefile.inc')
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 8827ada695..53d3b71ab3 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -3,21 +3,14 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c -romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c -romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c +romstage-y += util.c -ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c -ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c -ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c +ramstage-y += util.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c # Create and add the MRC cache to the cbfs image |