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| author | Duncan Laurie <dlaurie@chromium.org> | 2016-06-07 13:40:11 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-06-09 17:06:05 +0200 |
| commit | 8a14c39ac6c4ef3ed960d79aaf9e7c56b595f8f2 (patch) | |
| tree | b035c1e7bdedf3bac3dbcf409943994e190c1fd2 /src/soc/intel/common/Kconfig | |
| parent | ec00968f08e69f40ec978d2b6128764f4e4e12ea (diff) | |
soc/intel/common: Add LPSS I2C driver
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
DesignWare I2C block and have a similar configuration of that block.
This driver is ported from the Chromium depthcharge project where it
was ported from U-Boot originally, though it looks very different now.
From depthcharge it has been modified to fit into the coreboot I2C
driver model with platform_i2c_transfer() and use coreboot semantics
throughout including the stopwatch API for timeouts.
In order for this shared driver to work the SOC must:
1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
speed that the I2C controller core is running at.
2) Define the lpss_i2c_base_address() function to return the base
address for the specified bus. This could be either done by looking
up the PCI device or a static table if the controllers are not PCI
devices and just have a static base address.
The driver is usable in verstage/romstage/ramstage, though it does
require early initialization of the controller to set a temporary base
address if it is used outside of ramstage.
This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
ramstage environments by reading and writing both single bytes across
multiple segments as well as large blocks of data at once and with
different configured bus speeds.
While it does need specific configuration for each SOC this driver
should be able to work on all Intel SOCs currently in src/soc/intel.
Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15101
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/Kconfig')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index e64aabf426..fdd8f0436e 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -41,6 +41,21 @@ config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool default n +config SOC_INTEL_COMMON_LPSS_I2C + bool + default n + help + This driver supports the Intel Low Power Subsystem (LPSS) I2C + controllers that are based on Synopsys DesignWare IP. + +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + int + depends on SOC_INTEL_COMMON_LPSS_I2C + help + The clock speed that the I2C controller is running at, in MHz. + No default is set here as this is an SOC-specific value and must + be provided by the SOC when it selects this driver. + config SOC_SETS_MTRRS bool default n |