diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-24 15:23:40 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-10-26 01:50:36 +0200 |
| commit | aedbfc8f0917b332e648fe6c4333567bd8e58b0d (patch) | |
| tree | d56d052f2ecc6f6109a22060019e56c213a15249 /src/soc/intel/common/Kconfig | |
| parent | 5817a1555754709da92cae7f254d540e2b488cec (diff) | |
soc/intel/common: Enable support to write protect SPI flash range
Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.
BUG=chrome-os-partner:58896
Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/common/Kconfig')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8eae23b6e7..affec55718 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -9,6 +9,10 @@ config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n +config SOC_INTEL_COMMON_SPI_PROTECT + bool + default n + if CACHE_MRC_SETTINGS config MRC_SETTINGS_CACHE_BASE |