diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-17 10:50:47 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-07-01 10:26:12 +0000 |
| commit | a449290ca2d587d6eb9efca99d34c8a8658e3178 (patch) | |
| tree | 5836f0fc214b99d65d35ee5948d3a08c6c7e3b66 /src/soc/intel/cannonlake | |
| parent | 3891d272a0d5831c78464d2cd2bf89ef29d2cca1 (diff) | |
Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the
3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span
multiple targets.
Microcode updates present in
3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those
contain updates not present in the Intel repo. Those are presumably
early CPU samples that did not end up in products.
The following MCU are get a new revision:
old:
sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552
sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528
sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288
sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312
sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728
sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384
sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336
sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304
sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280
sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304
sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328
sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328
new:
sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552
sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504
sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288
sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336
sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728
sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408
sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360
sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304
sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328
sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456
sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 22 |
2 files changed, 20 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 679efce396..37e42f30e2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -16,6 +16,7 @@ config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS config SOC_INTEL_CANNONLAKE bool select SOC_INTEL_CANNONLAKE_BASE + select MICROCODE_BLOB_NOT_IN_BLOB_REPO help Intel Cannonlake support @@ -34,6 +35,7 @@ config SOC_INTEL_WHISKEYLAKE config SOC_INTEL_COMETLAKE bool select SOC_INTEL_CANNONLAKE_BASE + select MICROCODE_BLOB_UNDISCLOSED help Intel Cometlake support diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 5017410234..8a4a8b71f2 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -90,10 +90,24 @@ smm-y += gpio.c verstage-y += gpio.c endif -# Coffeelake U43e D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin -# Coffeelake H/S/E3 B0 U0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) +# Not yet in intel-microcode repo +#cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*) +else ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0a +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0b +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0c +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0d +else +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a +endif +else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c +else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y) +# TODO +endif CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include |