diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-24 13:50:56 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-27 03:01:31 +0000 |
| commit | 8c0dda218391afb95444d180333e552ba347aba7 (patch) | |
| tree | 709a05f8668d8e0d87a04462bc6d8c30af16ca47 /src/soc/intel/cannonlake | |
| parent | 1bfb74c14c91de5b745c8b8d6f0aabf8fb9ed008 (diff) | |
soc/intel/cannonlake: Align gpio_op.asl with TGL
Also drop gpio_common.h in favor of intelblocks/gpio_defs.h macros.
TEST=Able to build and boot CNL and CML platform.
1) Dump and disassemble DSDT, verify unified methods like GRXS,
GTXS etc. are there.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.
Change-Id: I78d712eeba56b9c098dc6a6f11e4e51cb2529b10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/gpio_op.asl | 21 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_common.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_defs.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h | 1 |
4 files changed, 11 insertions, 25 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 7f2a40cd46..9fa3dc4a86 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/gpio_defs.h> /* * Get GPIO Value @@ -11,7 +12,7 @@ Method (GRXS, 1, Serialized) { VAL0, 32 } - Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) + Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT Return (Local0) } @@ -27,7 +28,7 @@ Method (GTXS, 1, Serialized) { VAL0, 32 } - Local0 = GPIOTXSTATE_MASK & VAL0 + Local0 = PAD_CFG0_TX_STATE & VAL0 Return (Local0) } @@ -43,7 +44,7 @@ Method (STXS, 1, Serialized) { VAL0, 32 } - VAL0 |= GPIOTXSTATE_MASK + VAL0 |= PAD_CFG0_TX_STATE } /* @@ -57,7 +58,7 @@ Method (CTXS, 1, Serialized) { VAL0, 32 } - VAL0 &= ~GPIOTXSTATE_MASK + VAL0 &= ~PAD_CFG0_TX_STATE } /* @@ -76,8 +77,8 @@ Method (GPMO, 2, Serialized) { VAL0, 32 } - Local0 = ~GPIOPADMODE_MASK & VAL0 - Arg1 = (Arg1 << GPIOPADMODE_SHIFT) & GPIOPADMODE_MASK + Local0 = ~PAD_CFG0_MODE_MASK & VAL0 + Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK VAL0 = Local0 | Arg1 } @@ -97,9 +98,9 @@ Method (GTXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 &= ~GPIOTXBUFDIS_MASK + VAL0 &= ~PAD_CFG0_TX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 |= GPIOTXBUFDIS_MASK + VAL0 |= PAD_CFG0_TX_DISABLE } } @@ -119,8 +120,8 @@ Method (GRXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 &= ~GPIORXBUFDIS_MASK + VAL0 &= ~PAD_CFG0_RX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 |= GPIORXBUFDIS_MASK + VAL0 |= PAD_CFG0_RX_DISABLE } } diff --git a/src/soc/intel/cannonlake/include/soc/gpio_common.h b/src/soc/intel/cannonlake/include/soc/gpio_common.h deleted file mode 100644 index c11ef50403..0000000000 --- a/src/soc/intel/cannonlake/include/soc/gpio_common.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _SOC_CANNONLAKE_GPIO_COMMON_H_ -#define _SOC_CANNONLAKE_GPIO_COMMON_H_ - -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 -#define GPIOPADMODE_MASK 0xC00 -#define GPIOPADMODE_SHIFT 10 -#define GPIOTXBUFDIS_MASK 0x100 -#define GPIORXBUFDIS_MASK 0x200 - -#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 9b1690ea9d..e7769b5f31 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -6,7 +6,6 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#include <soc/gpio_common.h> #include <soc/gpio_soc_defs.h> #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h index a1f51d1d97..bd68b04f9b 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h @@ -6,7 +6,6 @@ #ifndef __ACPI__ #include <stddef.h> #endif -#include <soc/gpio_common.h> #include <soc/gpio_soc_defs_cnp_h.h> #define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ |