diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-12-11 13:25:00 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-12 13:22:58 +0000 |
| commit | 5f2d11484277e60439d2d62c02a5e7d60782bea3 (patch) | |
| tree | b2b92591a9342b894706540a3918e671cb455451 /src/soc/intel/cannonlake | |
| parent | 20fe24b4f76a6bc0623db51cbc5ea4ba1f833a44 (diff) | |
soc/intel/cannonlake: Rename SA_DEV_SLOT_DSP
Device 4 was introduced with a wrong name, since it is the SA Thermal
Subsystem and it does nothing have to do with DSP. Thus, rename it
accordingly.
Change-Id: I8edc764413df5f323098e60d0a3f0f87a7e656cb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60049
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pci_devs.h | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 32c5cbb8c6..fc12890410 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -59,9 +59,9 @@ static const struct slot_irq_constraints irq_constraints[] = { }, }, { - .slot = SA_DEV_SLOT_DSP, + .slot = SA_DEV_SLOT_TS, .fns = { - ANY_PIRQ(SA_DEVFN_DSP), + ANY_PIRQ(SA_DEVFN_TS), }, }, { diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 50ba6118e0..6998eb1022 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -34,9 +34,9 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) -#define SA_DEV_SLOT_DSP 0x04 -#define SA_DEVFN_DSP PCI_DEVFN(SA_DEV_SLOT_DSP, 0) -#define SA_DEV_DSP PCI_DEV(0, SA_DEV_SLOT_DSP, 0) +#define SA_DEV_SLOT_TS 0x04 +#define SA_DEVFN_TS PCI_DEVFN(SA_DEV_SLOT_TS, 0) +#define SA_DEV_TS PCI_DEV(0, SA_DEV_SLOT_TS, 0) #define SA_DEV_SLOT_IPU 0x05 #define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) |