src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

2 files changed, 267 insertions, 267 deletions

diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index fed8ac2199..578cbbf977 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -40,119 +40,119 @@ static struct {
 	u16 mchid;
 	const char *name;
 } mch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" },
-	{ PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_U_2, "Coffeelake U (2)" },
-	{ PCI_DEVICE_ID_INTEL_WHL_ID_W_4, "Whiskeylake W (4+2)" },
-	{ PCI_DEVICE_ID_INTEL_WHL_ID_W_2, "Whiskeylake W (2+2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_H_4, "Coffeelake-H (4)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_H_8, "Coffeelake-H (8+2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2, "Coffeelake-S DT(2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4, "Coffeelake-S DT(4)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, "Coffeelake-S DT(8+2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4, "Coffeelake-S WS(4+2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6, "Coffeelake-S WS(6+2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, "Coffeelake-S WS(8+2)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4, "Coffeelake-S S(4)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6, "Coffeelake-S S(6)" },
-	{ PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8, "Coffeelake-S S(8)" },
-	{ PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_4, "CometLake-S G0/G1 (4+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_S_G0G1_2, "CometLake-S G0/G1 (2+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_H_4_2, "CometLake-H (4+2)" },
-	{ PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },
+	{ PCI_DID_INTEL_CNL_ID_U, "Cannonlake-U" },
+	{ PCI_DID_INTEL_CNL_ID_Y, "Cannonlake-Y" },
+	{ PCI_DID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" },
+	{ PCI_DID_INTEL_CFL_ID_U_2, "Coffeelake U (2)" },
+	{ PCI_DID_INTEL_WHL_ID_W_4, "Whiskeylake W (4+2)" },
+	{ PCI_DID_INTEL_WHL_ID_W_2, "Whiskeylake W (2+2)" },
+	{ PCI_DID_INTEL_CFL_ID_H, "Coffeelake-H" },
+	{ PCI_DID_INTEL_CFL_ID_H_4, "Coffeelake-H (4)" },
+	{ PCI_DID_INTEL_CFL_ID_H_8, "Coffeelake-H (8+2)" },
+	{ PCI_DID_INTEL_CFL_ID_S, "Coffeelake-S" },
+	{ PCI_DID_INTEL_CFL_ID_S_DT_2, "Coffeelake-S DT(2)" },
+	{ PCI_DID_INTEL_CFL_ID_S_DT_4, "Coffeelake-S DT(4)" },
+	{ PCI_DID_INTEL_CFL_ID_S_DT_8, "Coffeelake-S DT(8+2)" },
+	{ PCI_DID_INTEL_CFL_ID_S_WS_4, "Coffeelake-S WS(4+2)" },
+	{ PCI_DID_INTEL_CFL_ID_S_WS_6, "Coffeelake-S WS(6+2)" },
+	{ PCI_DID_INTEL_CFL_ID_S_WS_8, "Coffeelake-S WS(8+2)" },
+	{ PCI_DID_INTEL_CFL_ID_S_S_4, "Coffeelake-S S(4)" },
+	{ PCI_DID_INTEL_CFL_ID_S_S_6, "Coffeelake-S S(6)" },
+	{ PCI_DID_INTEL_CFL_ID_S_S_8, "Coffeelake-S S(8)" },
+	{ PCI_DID_INTEL_CML_ULT, "CometLake-U (4+2)" },
+	{ PCI_DID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" },
+	{ PCI_DID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" },
+	{ PCI_DID_INTEL_CML_ULX, "CometLake-ULX (4+2)" },
+	{ PCI_DID_INTEL_CML_S, "CometLake-S (6+2)" },
+	{ PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2, "CometLake-S G0/G1/P0/P1 (6+2)" },
+	{ PCI_DID_INTEL_CML_S_P0P1_8_2, "CometLake-S P0/P1 (8+2)" },
+	{ PCI_DID_INTEL_CML_S_P0P1_10_2, "CometLake-S P0/P1 (10+2)" },
+	{ PCI_DID_INTEL_CML_S_G0G1_4, "CometLake-S G0/G1 (4+2)" },
+	{ PCI_DID_INTEL_CML_S_G0G1_2, "CometLake-S G0/G1 (2+2)" },
+	{ PCI_DID_INTEL_CML_H, "CometLake-H (6+2)" },
+	{ PCI_DID_INTEL_CML_H_4_2, "CometLake-H (4+2)" },
+	{ PCI_DID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },
 };
 
 static struct {
 	u16 lpcid;
 	const char *name;
 } pch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
-	{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
-	{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_H310, "Cannonlake-H H310" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_H370, "Cannonlake-H H370" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_Z390, "Cannonlake-H Z390" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_B360, "Cannonlake-H B360" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_C242, "Cannonlake-H C242" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_HM370, "Cannonlake-H HM370" },
-	{ PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" },
-	{ PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" },
-	{ PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" },
-	{ PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" },
-	{ PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" },
-	{ PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" },
-	{ PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" },
+	{ PCI_DID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
+	{ PCI_DID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
+	{ PCI_DID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
+	{ PCI_DID_INTEL_CNP_H_LPC_H310, "Cannonlake-H H310" },
+	{ PCI_DID_INTEL_CNP_H_LPC_H370, "Cannonlake-H H370" },
+	{ PCI_DID_INTEL_CNP_H_LPC_Z390, "Cannonlake-H Z390" },
+	{ PCI_DID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" },
+	{ PCI_DID_INTEL_CNP_H_LPC_B360, "Cannonlake-H B360" },
+	{ PCI_DID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" },
+	{ PCI_DID_INTEL_CNP_H_LPC_C242, "Cannonlake-H C242" },
+	{ PCI_DID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" },
+	{ PCI_DID_INTEL_CNP_H_LPC_HM370, "Cannonlake-H HM370" },
+	{ PCI_DID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" },
+	{ PCI_DID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" },
+	{ PCI_DID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" },
+	{ PCI_DID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" },
+	{ PCI_DID_INTEL_CMP_BASE_U_LPC, "Cometlake-U Base" },
+	{ PCI_DID_INTEL_CMP_SUPER_Y_LPC, "Cometlake-Y Super" },
+	{ PCI_DID_INTEL_CMP_H_LPC_HM470, "Cometlake-H HM470" },
+	{ PCI_DID_INTEL_CMP_H_LPC_WM490, "Cometlake-H WM490" },
+	{ PCI_DID_INTEL_CMP_H_LPC_QM480, "Cometlake-H QM480" },
+	{ PCI_DID_INTEL_CMP_H_LPC_W480, "Cometlake-H W480" },
+	{ PCI_DID_INTEL_CMP_H_LPC_H470, "Cometlake-H H470" },
+	{ PCI_DID_INTEL_CMP_H_LPC_Z490, "Cometlake-H Z490" },
+	{ PCI_DID_INTEL_CMP_H_LPC_Q470, "Cometlake-H Q470" },
 };
 
 static struct {
 	u16 igdid;
 	const char *name;
 } igd_table[] = {
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
-	{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, "Whiskeylake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT1_1, "Coffeelake-S GT1" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT1_2, "Coffeelake-S GT1" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CFL_S_GT2_5, "Coffeelake-S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" },
-	{ PCI_DEVICE_ID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" },
+	{ PCI_DID_INTEL_CNL_GT2_ULX_1, "Cannonlake ULX GT2" },
+	{ PCI_DID_INTEL_CNL_GT2_ULX_2, "Cannonlake ULX GT1.5" },
+	{ PCI_DID_INTEL_CNL_GT2_ULX_3, "Cannonlake ULX GT1" },
+	{ PCI_DID_INTEL_CNL_GT2_ULX_4, "Cannonlake ULX GT0.5" },
+	{ PCI_DID_INTEL_CNL_GT2_ULT_1, "Cannonlake ULT GT2" },
+	{ PCI_DID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" },
+	{ PCI_DID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" },
+	{ PCI_DID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
+	{ PCI_DID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2" },
+	{ PCI_DID_INTEL_WHL_GT1_ULT_1, "Whiskeylake ULT GT1" },
+	{ PCI_DID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" },
+	{ PCI_DID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" },
+	{ PCI_DID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" },
+	{ PCI_DID_INTEL_CFL_S_GT1_1, "Coffeelake-S GT1" },
+	{ PCI_DID_INTEL_CFL_S_GT1_2, "Coffeelake-S GT1" },
+	{ PCI_DID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" },
+	{ PCI_DID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" },
+	{ PCI_DID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" },
+	{ PCI_DID_INTEL_CFL_S_GT2_4, "Coffeelake-S GT2" },
+	{ PCI_DID_INTEL_CFL_S_GT2_5, "Coffeelake-S GT2" },
+	{ PCI_DID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" },
+	{ PCI_DID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" },
+	{ PCI_DID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" },
+	{ PCI_DID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" },
+	{ PCI_DID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" },
+	{ PCI_DID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
+	{ PCI_DID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
+	{ PCI_DID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
+	{ PCI_DID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
+	{ PCI_DID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
+	{ PCI_DID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
+	{ PCI_DID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" },
+	{ PCI_DID_INTEL_CML_GT1_S_1, "CometLake S GT1" },
+	{ PCI_DID_INTEL_CML_GT1_S_2, "CometLake S GT1" },
+	{ PCI_DID_INTEL_CML_GT2_S_1, "CometLake S GT2" },
+	{ PCI_DID_INTEL_CML_GT2_S_2, "CometLake S GT2" },
+	{ PCI_DID_INTEL_CML_GT2_S_G0, "CometLake S GT2 G0" },
+	{ PCI_DID_INTEL_CML_GT2_S_P0, "CometLake S GT2 P0" },
+	{ PCI_DID_INTEL_CML_GT1_H_1, "CometLake H GT1" },
+	{ PCI_DID_INTEL_CML_GT1_H_2, "CometLake H GT1" },
+	{ PCI_DID_INTEL_CML_GT2_H_1, "CometLake H GT2" },
+	{ PCI_DID_INTEL_CML_GT2_H_2, "CometLake H GT2" },
+	{ PCI_DID_INTEL_CML_GT2_H_R0, "CometLake H GT2 R0" },
+	{ PCI_DID_INTEL_CML_GT2_H_R1, "CometLake H GT2 R1" },
 
 };
 
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c
index ade1ef6277..bd5fefbdd3 100644
--- a/src/soc/intel/cannonlake/vr_config.c
+++ b/src/soc/intel/cannonlake/vr_config.c
@@ -178,108 +178,108 @@ static uint16_t load_table(const struct vr_lookup *tbl,
  *  The above values in () are for baseline.
  */
 
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CNL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_Y) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CNL_ID_Y) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(13, 34, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_WHL_ID_W_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_WHL_ID_W_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_U_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(8.5, 64, 64, 64) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_8) { /* undocumented */
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H_8) { /* undocumented */
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 128, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_H_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 0, 0) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_2) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 35, 35) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 58, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
 	{ 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_DT_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_WS_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 133, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CFL_ID_S_S_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 45, 45) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT_6_2) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(6, 85, 31, 31) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(6, 70, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_ULT_2_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(6, 35, 31, 31) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_H_8_2) {
 	{ 65, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) },
 	{ 65, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 192, 32, 32) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 165, 32, 32) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_H) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 32, 32) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_H_4_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_H_4_2) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 105, 32, 32) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 86, 32, 32) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_P0P1_8_2) {
 	{125, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) },
 	{125, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
@@ -288,7 +288,7 @@ VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_P0P1_10_2) {
 	{125, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 245, 35, 35) },
 	{125, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 210, 35, 35) },
@@ -297,304 +297,304 @@ VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
 	{  0, performance,  VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
 	{  0, baseline,     VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 140, 35, 35) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_4) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 102, 35, 35) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 65, 35, 35) },
 };
-VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) {
+VR_CONFIG_ICC(PCI_DID_INTEL_CML_S_G0G1_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 35, 35) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 35, 35) },
 };
 
 static const struct vr_lookup vr_config_icc[] = {
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_U),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CNL_ID_Y),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_WHL_ID_W_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_U_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H_8_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_H_4_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4),
-	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2),
-};
-
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U) {
+	VR_REFITEM_ICC(PCI_DID_INTEL_CNL_ID_U),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CNL_ID_Y),
+	VR_REFITEM_ICC(PCI_DID_INTEL_WHL_ID_W_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_WHL_ID_W_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_U),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_U_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_H_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_DT_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT_6_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_ULT_2_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_H_8_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_H),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_H_4_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_P0P1_8_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_P0P1_10_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_4),
+	VR_REFITEM_ICC(PCI_DID_INTEL_CML_S_G0G1_2),
+};
+
+VR_CONFIG_LL(PCI_DID_INTEL_CNL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_Y) {
+VR_CONFIG_LL(PCI_DID_INTEL_CNL_ID_Y) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_4) { /* unspecified */
+VR_CONFIG_LL(PCI_DID_INTEL_WHL_ID_W_4) { /* unspecified */
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 0, 0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_2) { /* unspecified */
+VR_CONFIG_LL(PCI_DID_INTEL_WHL_ID_W_2) { /* unspecified */
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 0, 0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_U_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_H_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_DT_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_WS_6) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_6) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CFL_ID_S_S_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT_6_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_ULT_2_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_H_8_2) {
 	{ 0, value_not_set,  VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_H) {
 	{ 0, value_not_set,  VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_H_4_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_H_4_2) {
 	{ 0, value_not_set,  VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 2.7, 2.7) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_P0P1_8_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_P0P1_10_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
 	{125, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.1, 4.0, 4.0) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
-VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) {
+VR_CONFIG_LL(PCI_DID_INTEL_CML_S_G0G1_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.7, 4.0, 4.0) },
 };
 
 
 static const struct vr_lookup vr_config_ll[] = {
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CNL_ID_Y),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_WHL_ID_W_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_U_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H_8_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_H_4_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4),
-	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2),
-};
-
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
+	VR_REFITEM_LL(PCI_DID_INTEL_CNL_ID_U),
+	VR_REFITEM_LL(PCI_DID_INTEL_CNL_ID_Y),
+	VR_REFITEM_LL(PCI_DID_INTEL_WHL_ID_W_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_WHL_ID_W_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_U),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_U_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_H_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_DT_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_LL(PCI_DID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT_6_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_ULT_2_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_H_8_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_H),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_H_4_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_P0P1_8_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_P0P1_10_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_4),
+	VR_REFITEM_LL(PCI_DID_INTEL_CML_S_G0G1_2),
+};
+
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_H) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_2) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_4) {
 	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
 	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
 	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_6) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_S_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_WS_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CFL_ID_S_DT_8) {
 	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT) {
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_6_2) {
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_ULT_2_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(4, 24, 22, 22) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_8_2) {
 	{ 65, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 146, 25, 25) },
 	{ 65, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 117, 25, 25) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10,  86, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_H) {
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_4_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_H_4_2) {
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 60, 25, 25) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_P0P1_8_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_P0P1_10_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 175, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2) {
 	{125, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 132, 28, 28) },
 	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 104, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_4) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 68, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 42, 28, 28) },
 };
-VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2) {
+VR_CONFIG_TDC(PCI_DID_INTEL_CML_S_G0G1_2) {
 	{ 36, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 38, 28, 28) },
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 25, 28, 28) },
 };
 
 static const struct vr_lookup vr_config_tdc[] = {
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_H),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_H_4_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_4),
-	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_H),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CFL_ID_S_DT_8),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_6_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_ULT_2_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_8_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_H),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_H_4_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_P0P1_8_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_P0P1_10_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_4),
+	VR_REFITEM_TDC(PCI_DID_INTEL_CML_S_G0G1_2),
 };
 
 static uint16_t get_sku_voltagelimit(int domain)