diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2019-01-11 13:44:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-16 12:55:17 +0000 |
| commit | 41169def5c9a3ad2456e70dd5032a060ad786c69 (patch) | |
| tree | 6f979a00e282b928566044503cc7f72385363b26 /src/soc/intel/cannonlake | |
| parent | c896e92eaad8e255c1cef65b9da2367742a61e5f (diff) | |
soc/intel/cannonlake: Access conf pointer only if its not null
conf pointer could be null, access it only if its not null.
Foundby=klocwork
BUG=N/A
TEST=N/A
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216
Reviewed-on: https://review.coreboot.org/c/30860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index d0ed3ba150..f987f8b42f 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -234,7 +234,7 @@ static void configure_isst(void) config_t *conf = dev->chip_info; msr_t msr; - if (conf->speed_shift_enable) { + if (conf && conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP * is supported or not. coreboot needs to configure MSR 0x1AA @@ -267,7 +267,7 @@ static void configure_misc(void) msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - if (conf->eist_enable) + if (conf && conf->eist_enable) cpu_enable_eist(); else cpu_disable_eist(); |