summaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2021-06-21 19:25:17 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-06-23 08:26:17 +0000
commit3b374bebac10ccf08a4741e86b03d4353072d625 (patch)
treebf5cfd681aeebc4f0c2d9ebf4a08d382e6bac0e4 /src/soc/intel/cannonlake
parent5dea3162506270e713347c9ca67717d292007cbd (diff)
soc/intel/cannonlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I64ab77bc49d93aca1da0126d849e69ff75b182a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55726 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 7f1476c39c..89293442ba 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -300,13 +300,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
- if (dev) {
- if (!xdci_can_enable())
- dev->enabled = 0;
- params->XdciEnable = dev->enabled;
- } else
- params->XdciEnable = 0;
+ if (!xdci_can_enable())
+ devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
+ params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
/* Set Debug serial port */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;