diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-06-10 14:00:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:17:16 +0000 |
| commit | 1a86cda6dbacfbae285fa3d44b3f67bea95367e3 (patch) | |
| tree | 796c741837012098d19cb049dd6debe091f385af /src/soc/intel/cannonlake | |
| parent | d97591c34571b66157c540355457c4fea794a611 (diff) | |
soc/intel: Provide SPD manufacturer ID and module type to SMBIOS
The DIMM manufacturing ID was not being initialized and so the DIMMs
were not described in SMBIOS tables properly.
The module type can also be provided, but the SMBIOS code expects
SPD module type values from DDR2 so the DDR3/4 values are adjusted
before sending to SMBIOS.
BUG=b:134897498
BRANCH=sarien
TEST=dump and compare with dmidecode
BEFORE:
Type: DDR4
Manufacturer: Unknown (0)
Form Factor: Unknown
AFTER:
Type: DDR4
Manufacturer: Hynix/Hyundai
Form Factor: SODIMM
Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index fa530a29a6..9dadb2d14e 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -116,7 +116,9 @@ static void save_dimm_info(void) src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth, memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport); + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); index++; } } |