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authorSubrata Banik <subrata.banik@intel.com>2020-09-29 13:55:50 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-10-03 04:18:32 +0000
commit1366e4438d07c2de905454421e18d1e5f68de47d (patch)
treeeebb4803b4e0ebada8372d3482fa2d5ae3c93b6f /src/soc/intel/cannonlake
parent18b1984f8666fbbac40b08c8de86cef15a9d9a9b (diff)
soc/intel: Move pch_enable_ioapic() to common code
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
-rw-r--r--src/soc/intel/cannonlake/lpc.c24
1 files changed, 1 insertions, 23 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 50af9ee360..9d36f32970 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -90,28 +90,6 @@ static void soc_mirror_dmi_pcr_io_dec(void)
soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
}
-static void pch_enable_ioapic(const struct device *dev)
-{
- u32 reg32;
- /* PCH-LP has 120 redirection entries */
- const int redir_entries = 120;
-
- set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
-
- /* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
-
- reg32 &= ~0x00ff0000;
- reg32 |= (redir_entries - 1) << 16;
-
- io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
-
- /*
- * Select Boot Configuration register (0x03) and
- * use Processor System Bus (0x01) to deliver interrupts.
- */
- io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
-}
/*
* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved
@@ -207,7 +185,7 @@ void lpc_soc_init(struct device *dev)
lpc_set_serirq_mode(config->serirq_mode);
/* Interrupt configuration */
- pch_enable_ioapic(dev);
+ pch_enable_ioapic();
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);