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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-03 07:03:39 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-09 07:33:18 +0000 |
| commit | c9871505f115f0e5722bf23b13f4390c8d76d0da (patch) | |
| tree | 99d1450f8a6f55825a07c5275c55f7234123894c /src/soc/intel/cannonlake | |
| parent | c563d34fc14dfb4e57e1841725dfb778e623e681 (diff) | |
intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is
confusing. Previously the region was shared for heap and stack,
starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs.
Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of
stack guards and reduces amount of reserved CAR for bootblock and
verstage, as the new allocation in .bss is only taken in romstage.
BUG=b:140268415
Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
0 files changed, 0 insertions, 0 deletions