diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-05-07 16:04:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-14 15:06:15 +0000 |
| commit | 1085fee761b381bbc2f9d18fb9cdc8a9e1c90884 (patch) | |
| tree | d43761b7082ae3767b92a6d973b4b0af7fd1455a /src/soc/intel/cannonlake | |
| parent | 6b95507ec5b087658178a325bdc68570bc48bb20 (diff) | |
soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G
This change sets the base for MMIO above 4G to TOUDD. It matches what
is used by resource allocator if MMIO resources are allocated above 4G
and also matches the expectation in northbridge.asl. This change
also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now
unused.
BUG=b:149186922
TEST=Verified that kernel does not complain about MMIO windows above
4G.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/iomap.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index ec60d0bb8a..9d13d84d3a 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -54,7 +54,6 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 -#define ABOVE_4GB_MEM_BASE_ADDRESS (256ULL * GiB) #define ABOVE_4GB_MEM_BASE_SIZE (256ULL * GiB) /* PTT registers */ |