diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-28 23:24:57 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-03 13:48:56 +0000 |
| commit | 92b78157022b0bd0777f84138f26ba879cef1028 (patch) | |
| tree | 179f0cf2f69ba7e9341479bc5397a64cefa73f82 /src/soc/intel/cannonlake | |
| parent | cfd32241978840e8d464a089d59a093ad0301d6f (diff) | |
soc/intel/cannonlake: Forbid FSP from disabling HECI1
The functionality of disabling HECI1 device has been moved from the
FSP to coreboot (using `DISABLE_HECI1_AT_PRE_BOOT` config), hence,
always set the `Heci1Disabled` UPD to `0`.
BUG=none
TEST=Boot to OS, verify HECI1 is disabled on hatch system
using coreboot when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index af356d1985..1726cd7c20 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -586,9 +586,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ScsUfsEnabled = is_devfn_enabled(PCH_DEVFN_UFS); params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3); -#if !CONFIG(HECI_DISABLE_USING_SMM) - params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); -#endif + /* + * coreboot will handle disabling of HECI1 device if `DISABLE_HECI1_AT_PRE_BOOT` + * config is selected hence, don't let FSP to disable the HECI1 device and set + * the `Heci1Disabled` UPD to `0`. + */ + params->Heci1Disabled = 0; params->Device4Enable = config->Device4Enable; /* Teton Glacier hybrid storage support */ |