diff options
| author | Felix Singer <felixsinger@posteo.net> | 2022-12-16 04:40:39 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-12-23 10:17:34 +0000 |
| commit | 86bc2e708dc2600c5611b6573d43645e7d57e561 (patch) | |
| tree | 54b589e40a81ee74915df4ed68a6a13c944bc17d /src/soc/intel/cannonlake | |
| parent | 372573eaff0f757f004de2f4fb3f688de93bbbba (diff) | |
tree: Replace Or(a,b,c) with ASL 2.0 syntax
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where
possible.
Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index e36824e7e5..5e8fb33f75 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -53,7 +53,7 @@ Scope (\_SB.PCI0) { PGEN = 1 // Enable PG /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) + PMCR |= 3 ^TEMP = PMCR } @@ -223,7 +223,7 @@ Scope (\_SB.PCI0) { PGEN = 1 /* Enable PG */ /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) + PMCR |= 3 ^TEMP = PMCR #if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) |