soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions

- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.

- Add gpio pin definitions for CNP-H and related changes.

- Add gpio device name, host software ownership reg offset for CNP-H.

BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
      RVP11 and verify power management, IO device functionalities
      work fine.

Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

11 files changed, 985 insertions, 14 deletions

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index dcec9bcc8f..e39aaadd7e 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -10,7 +10,7 @@ config SOC_INTEL_COFFEELAKE
 	help
 	  Intel Coffeelake support
 
-config CANNONLAKE_SOC_PCH_H
+config SOC_INTEL_CANNONLAKE_PCH_H
 	bool
 	default n
 	help
@@ -165,7 +165,7 @@ config NHLT_DA7219
 
 config MAX_ROOT_PORTS
 	int
-	default 24 if CANNONLAKE_SOC_PCH_H
+	default 24 if SOC_INTEL_CANNONLAKE_PCH_H
 	default 16
 
 config SMM_TSEG_SIZE
@@ -204,7 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 
 config SOC_INTEL_I2C_DEV_MAX
 	int
-	default 4 if CANNONLAKE_SOC_PCH_H
+	default 4 if SOC_INTEL_CANNONLAKE_PCH_H
 	default 6
 
 # Clock divider parameters for 115200 baud rate
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index f49add01e0..e95d04f274 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -13,7 +13,6 @@ bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += gpio.c
 bootblock-y += gspi.c
 bootblock-y += i2c.c
 bootblock-y += memmap.c
@@ -23,7 +22,6 @@ bootblock-y += p2sb.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c
 
 romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
-romstage-y += gpio.c
 romstage-y += gspi.c
 romstage-y += i2c.c
 romstage-y += lpc.c
@@ -38,10 +36,8 @@ ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
-ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += gspi.c
-ramstage-y += gpio.c
 ramstage-y += i2c.c
 ramstage-y += lockdown.c
 ramstage-y += lpc.c
@@ -58,7 +54,6 @@ ramstage-$(CONFIG_UART_DEBUG) += uart.c
 ramstage-y += vr_config.c
 ramstage-y += sd.c
 
-smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmutil.c
 smm-y += smihandler.c
@@ -77,6 +72,18 @@ verstage-y += pmutil.c
 verstage-y += spi.c
 verstage-$(CONFIG_UART_DEBUG) += uart.c
 
+ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
+bootblock-y += gpio_cnp_h.c
+romstage-y += gpio_cnp_h.c
+ramstage-y += gpio_cnp_h.c
+smm-y += gpio_cnp_h.c
+else
+bootblock-y += gpio.c
+romstage-y += gpio.c
+ramstage-y += gpio.c
+smm-y += gpio.c
+endif
+
 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
 
diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
new file mode 100644
index 0000000000..6e6eccf361
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs_cnp_h.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+
+Device (GPIO)
+{
+	Name (_HID, "INT3450")
+	Name (_UID, 0)
+	Name (_DDN, "GPIO Controller")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM2)
+		Memory32Fixed (ReadWrite, 0, 0, COM3)
+		Memory32Fixed (ReadWrite, 0, 0, COM4)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+			{ GPIO_IRQ14 }
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		/* GPIO Community 0 */
+		CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+		Store (^^PCRB (PID_GPIOCOM0), BAS0)
+		Store (GPIO_BASE_SIZE, LEN0)
+
+		/* GPIO Community 1 */
+		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+		Store (^^PCRB (PID_GPIOCOM1), BAS1)
+		Store (GPIO_BASE_SIZE, LEN1)
+
+		/* GPIO Community 2 */
+		CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
+		CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
+		Store (^^PCRB (PID_GPIOCOM2), BAS2)
+		Store (GPIO_BASE_SIZE, LEN2)
+
+		/* GPIO Community 3 */
+		CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
+		CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
+		Store (^^PCRB (PID_GPIOCOM3), BAS3)
+		Store (GPIO_BASE_SIZE, LEN3)
+
+
+		/* GPIO Community 4 */
+		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+		Store (^^PCRB (PID_GPIOCOM4), BAS4)
+		Store (GPIO_BASE_SIZE, LEN4)
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0xF)
+	}
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+	/* GPIO Community 0 */
+	If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
+	{
+		Store (PID_GPIOCOM0, Local0)
+		Subtract (Arg0, GPP_A0, Local1)
+	}
+	/* GPIO Community 1 */
+	If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7)))
+	{
+		Store (PID_GPIOCOM1, Local0)
+		Subtract (Arg0, GPP_C0, Local1)
+	}
+	/* GPIO Community 3*/
+	If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23)))
+	{
+		Store (PID_GPIOCOM3, Local0)
+		Subtract (Arg0, GPP_K0, Local1)
+	}
+	/* GPIO Community 4*/
+	If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11)))
+	{
+		Store (PID_GPIOCOM4, Local0)
+		Subtract (Arg0, GPP_I0, Local1)
+	}
+	Store (PCRB (Local0), Local2)
+	Add (Local2, PAD_CFG_BASE, Local2)
+	Return (Add (Local2, Multiply (Local1, 16)))
+}
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
+
+	Return (Local0)
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index ff323c40a3..49b5f6e509 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -33,7 +33,11 @@
 #include "scs.asl"
 
 /* GPIO controller */
+#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#include "gpio_cnp_h.asl"
+#else
 #include "gpio.asl"
+#endif
 
 /* LPC 0:1f.0 */
 #include "lpc.asl"
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index ca021c2b7d..74cb833bf6 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -24,12 +24,18 @@
 #include <stdint.h>
 #include <soc/gpio.h>
 #include <soc/pch.h>
-#include <soc/gpio_defs.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <soc/serialio.h>
 #include <soc/usb.h>
 #include <soc/vr_config.h>
+#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#include <soc/gpio_defs_cnp_h.h>
+#else
+#include <soc/gpio_defs.h>
+#endif
+
+
 
 struct soc_intel_cannonlake_config {
 
diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
new file mode 100644
index 0000000000..939a38e6a8
--- /dev/null
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct reset_mapping rst_map_com0[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
+};
+
+static const struct pad_group cnl_community0_groups[] = {
+	INTEL_GPP(GPP_A0, GPP_A0, GPP_A23),		/* GPP_A */
+	INTEL_GPP(GPP_A0, GPP_B0, GPP_B23),		/* GPP_B */
+};
+
+static const struct pad_group cnl_community1_groups[] = {
+	INTEL_GPP(GPP_C0, GPP_C0, GPP_C23),		/* GPP_C */
+	INTEL_GPP(GPP_C0, GPP_D0, GPP_D23),		/* GPP_D */
+	INTEL_GPP(GPP_C0, GPP_G0, GPP_G7),		/* GPP_G */
+};
+
+static const struct pad_group cnl_community2_groups[] = {
+	INTEL_GPP(GPD0, GPD0, GPD11),			/* GPD */
+};
+
+static const struct pad_group cnl_community3_groups[] = {
+	INTEL_GPP(GPP_K0, GPP_K0, GPP_K23),		/* GPP_K*/
+	INTEL_GPP(GPP_K0, GPP_H0, GPP_H23),		/* GPP_H */
+	INTEL_GPP(GPP_K0, GPP_E0, GPP_E12),		/* GPP_E */
+	INTEL_GPP(GPP_K0, GPP_F0, GPP_F23),		/* GPP_F */
+};
+
+static const struct pad_group cnl_community4_groups[] = {
+	INTEL_GPP(GPP_I0, GPP_I0, GPP_I14),		/* GPP_I */
+	INTEL_GPP(GPP_I0, GPP_J0, GPP_J11),		/* GPP_J */
+};
+
+static const struct pad_community cnl_communities[] = {
+	{ /* GPP A, B */
+		.port = PID_GPIOCOM0,
+		.first_pad = GPP_A0,
+		.last_pad = GPP_B23,
+		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_AB",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map_com0,
+		.num_reset_vals = ARRAY_SIZE(rst_map_com0),
+		.groups = cnl_community0_groups,
+		.num_groups = ARRAY_SIZE(cnl_community0_groups),
+	}, { /* GPP C, D, G */
+		.port = PID_GPIOCOM1,
+		.first_pad = GPP_C0,
+		.last_pad = GPP_G7,
+		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_CDG",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community1_groups,
+		.num_groups = ARRAY_SIZE(cnl_community1_groups),
+	}, { /* GPD */
+		.port = PID_GPIOCOM2,
+		.first_pad = GPD0,
+		.last_pad = GPD11,
+		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPD",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community2_groups,
+		.num_groups = ARRAY_SIZE(cnl_community2_groups),
+	}, { /* GPP K, H, E, F */
+		.port = PID_GPIOCOM3,
+		.first_pad = GPP_K0,
+		.last_pad = GPP_F23,
+		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_KHEF",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community3_groups,
+		.num_groups = ARRAY_SIZE(cnl_community3_groups),
+	}, { /* GPP I, J */
+		.port = PID_GPIOCOM4,
+		.first_pad = GPP_I0,
+		.last_pad = GPP_J11,
+		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_IJ",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = cnl_community4_groups,
+		.num_groups = ARRAY_SIZE(cnl_community4_groups),
+	}
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(cnl_communities);
+	return cnl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+	static const struct pmc_to_gpio_route routes[] = {
+		{ PMC_GPP_A, GPP_A },
+		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_C, GPP_C },
+		{ PMC_GPP_D, GPP_D },
+		{ PMC_GPP_E, GPP_E },
+		{ PMC_GPP_F, GPP_F },
+		{ PMC_GPP_G, GPP_G },
+		{ PMC_GPP_H, GPP_H },
+		{ PMC_GPP_I, GPP_I },
+		{ PMC_GPP_J, GPP_J },
+		{ PMC_GPP_K, GPP_K },
+		{ PMC_GPD, GPD },
+	};
+	*num = ARRAY_SIZE(routes);
+	return routes;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index 2d9f3d7120..cbc230a6a4 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,9 +16,14 @@
 #ifndef _SOC_CANNONLAKE_GPIO_H_
 #define _SOC_CANNONLAKE_GPIO_H_
 
-#include <soc/gpio_defs.h>
-#include <intelblocks/gpio.h>
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#include <soc/gpio_defs_cnp_h.h>
+#define CROS_GPIO_DEVICE_NAME	"INT3450:00"
+#else
+#include <soc/gpio_defs.h>
 #define CROS_GPIO_DEVICE_NAME	"INT34BB:00"
+#endif
+#include <intelblocks/gpio.h>
 
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
new file mode 100644
index 0000000000..ab04142551
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
@@ -0,0 +1,329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_
+#define _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs_cnp_h.h>
+
+
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n)	\
+		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+
+#define NUM_GPI_STATUS_REGS	\
+		((NUM_GPIO_COM0_GPI_REGS) +\
+		(NUM_GPIO_COM1_GPI_REGS) +\
+		(NUM_GPIO_COM2_GPI_REGS) +\
+		(NUM_GPIO_COM3_GPI_REGS) +\
+		(NUM_GPIO_COM4_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group A */
+#define GPP_A0_IRQ				0x18
+#define GPP_A1_IRQ				0x19
+#define GPP_A2_IRQ				0x1a
+#define GPP_A3_IRQ				0x1b
+#define GPP_A4_IRQ				0x1c
+#define GPP_A5_IRQ				0x1d
+#define GPP_A6_IRQ				0x1e
+#define GPP_A7_IRQ				0x1f
+#define GPP_A8_IRQ				0x20
+#define GPP_A9_IRQ				0x21
+#define GPP_A10_IRQ				0x22
+#define GPP_A11_IRQ				0x23
+#define GPP_A12_IRQ				0x24
+#define GPP_A13_IRQ				0x25
+#define GPP_A14_IRQ				0x26
+#define GPP_A15_IRQ				0x27
+#define GPP_A16_IRQ				0x28
+#define GPP_A17_IRQ				0x29
+#define GPP_A18_IRQ				0x2a
+#define GPP_A19_IRQ				0x2b
+#define GPP_A20_IRQ				0x2c
+#define GPP_A21_IRQ				0x2d
+#define GPP_A22_IRQ				0x2e
+#define GPP_A23_IRQ				0x2f
+/* Group B */
+#define GPP_B0_IRQ				0x30
+#define GPP_B1_IRQ				0x31
+#define GPP_B2_IRQ				0x32
+#define GPP_B3_IRQ				0x33
+#define GPP_B4_IRQ				0x34
+#define GPP_B5_IRQ				0x35
+#define GPP_B6_IRQ				0x36
+#define GPP_B7_IRQ				0x37
+#define GPP_B8_IRQ				0x38
+#define GPP_B9_IRQ				0x39
+#define GPP_B10_IRQ				0x3a
+#define GPP_B11_IRQ				0x3b
+#define GPP_B12_IRQ				0x3c
+#define GPP_B13_IRQ				0x3d
+#define GPP_B14_IRQ				0x3e
+#define GPP_B15_IRQ				0x3f
+#define GPP_B16_IRQ				0x40
+#define GPP_B17_IRQ				0x41
+#define GPP_B18_IRQ				0x42
+#define GPP_B19_IRQ				0x43
+#define GPP_B20_IRQ				0x44
+#define GPP_B21_IRQ				0x45
+#define GPP_B22_IRQ				0x46
+#define GPP_B23_IRQ				0x47
+/* Group C */
+#define GPP_C0_IRQ				0x48
+#define GPP_C1_IRQ				0x49
+#define GPP_C2_IRQ				0x4a
+#define GPP_C3_IRQ				0x4b
+#define GPP_C4_IRQ				0x4c
+#define GPP_C5_IRQ				0x4d
+#define GPP_C6_IRQ				0x4e
+#define GPP_C7_IRQ				0x4f
+#define GPP_C8_IRQ				0x50
+#define GPP_C9_IRQ				0x51
+#define GPP_C10_IRQ				0x52
+#define GPP_C11_IRQ				0x53
+#define GPP_C12_IRQ				0x54
+#define GPP_C13_IRQ				0x55
+#define GPP_C14_IRQ				0x56
+#define GPP_C15_IRQ				0x57
+#define GPP_C16_IRQ				0x58
+#define GPP_C17_IRQ				0x59
+#define GPP_C18_IRQ				0x5a
+#define GPP_C19_IRQ				0x5b
+#define GPP_C20_IRQ				0x5c
+#define GPP_C21_IRQ				0x5d
+#define GPP_C22_IRQ				0x5e
+#define GPP_C23_IRQ				0x5f
+/* Group D */
+#define GPP_D0_IRQ				0x60
+#define GPP_D1_IRQ				0x61
+#define GPP_D2_IRQ				0x62
+#define GPP_D3_IRQ				0x63
+#define GPP_D4_IRQ				0x64
+#define GPP_D5_IRQ				0x65
+#define GPP_D6_IRQ				0x66
+#define GPP_D7_IRQ				0x67
+#define GPP_D8_IRQ				0x68
+#define GPP_D9_IRQ				0x69
+#define GPP_D10_IRQ				0x6a
+#define GPP_D11_IRQ				0x6b
+#define GPP_D12_IRQ				0x6c
+#define GPP_D13_IRQ				0x6d
+#define GPP_D14_IRQ				0x6e
+#define GPP_D15_IRQ				0x6f
+#define GPP_D16_IRQ				0x70
+#define GPP_D17_IRQ				0x71
+#define GPP_D18_IRQ				0x72
+#define GPP_D19_IRQ				0x73
+#define GPP_D20_IRQ				0x74
+#define GPP_D21_IRQ				0x75
+#define GPP_D22_IRQ				0x76
+#define GPP_D23_IRQ				0x77
+/* Group E */
+#define GPP_E0_IRQ				0x18
+#define GPP_E1_IRQ				0x19
+#define GPP_E2_IRQ				0x1a
+#define GPP_E3_IRQ				0x1b
+#define GPP_E4_IRQ				0x1c
+#define GPP_E5_IRQ				0x1d
+#define GPP_E6_IRQ				0x1e
+#define GPP_E7_IRQ				0x1f
+#define GPP_E8_IRQ				0x20
+#define GPP_E9_IRQ				0x21
+#define GPP_E10_IRQ				0x22
+#define GPP_E11_IRQ				0x23
+#define GPP_E12_IRQ				0x24
+#define GPP_E13_IRQ				0x25
+#define GPP_E14_IRQ				0x26
+#define GPP_E15_IRQ				0x27
+#define GPP_E16_IRQ				0x28
+#define GPP_E17_IRQ				0x29
+#define GPP_E18_IRQ				0x2a
+#define GPP_E19_IRQ				0x2b
+#define GPP_E20_IRQ				0x2c
+#define GPP_E21_IRQ				0x2d
+#define GPP_E22_IRQ				0x2e
+#define GPP_E23_IRQ				0x2f
+/* Group F */
+#define GPP_F0_IRQ				0x30
+#define GPP_F1_IRQ				0x31
+#define GPP_F2_IRQ				0x32
+#define GPP_F3_IRQ				0x33
+#define GPP_F4_IRQ				0x34
+#define GPP_F5_IRQ				0x35
+#define GPP_F6_IRQ				0x36
+#define GPP_F7_IRQ				0x37
+#define GPP_F8_IRQ				0x38
+#define GPP_F9_IRQ				0x39
+#define GPP_F10_IRQ				0x3a
+#define GPP_F11_IRQ				0x3b
+#define GPP_F12_IRQ				0x3c
+#define GPP_F13_IRQ				0x3d
+#define GPP_F14_IRQ				0x3e
+#define GPP_F15_IRQ				0x3f
+#define GPP_F16_IRQ				0x40
+#define GPP_F17_IRQ				0x41
+#define GPP_F18_IRQ				0x42
+#define GPP_F19_IRQ				0x43
+#define GPP_F20_IRQ				0x44
+#define GPP_F21_IRQ				0x45
+#define GPP_F22_IRQ				0x46
+#define GPP_F23_IRQ				0x47
+/* Group G */
+#define GPP_G0_IRQ				0x6c
+#define GPP_G1_IRQ				0x6d
+#define GPP_G2_IRQ				0x6e
+#define GPP_G3_IRQ				0x6f
+#define GPP_G4_IRQ				0x70
+#define GPP_G5_IRQ				0x71
+#define GPP_G6_IRQ				0x72
+#define GPP_G7_IRQ				0x73
+/* Group GPD */
+#define GPD0_IRQ				0x60
+#define GPD1_IRQ				0x61
+#define GPD2_IRQ				0x62
+#define GPD3_IRQ				0x63
+#define GPD4_IRQ				0x64
+#define GPD5_IRQ				0x65
+#define GPD6_IRQ				0x66
+#define GPD7_IRQ				0x67
+#define GPD8_IRQ				0x68
+#define GPD9_IRQ				0x69
+#define GPD10_IRQ				0x6a
+#define GPD11_IRQ				0x6b
+/* Group H */
+#define GPP_H0_IRQ				0x48
+#define GPP_H1_IRQ				0x49
+#define GPP_H2_IRQ				0x4a
+#define GPP_H3_IRQ				0x4b
+#define GPP_H4_IRQ				0x4c
+#define GPP_H5_IRQ				0x4d
+#define GPP_H6_IRQ				0x4e
+#define GPP_H7_IRQ				0x4f
+#define GPP_H8_IRQ				0x50
+#define GPP_H9_IRQ				0x51
+#define GPP_H10_IRQ				0x52
+#define GPP_H11_IRQ				0x53
+#define GPP_H12_IRQ				0x54
+#define GPP_H13_IRQ				0x55
+#define GPP_H14_IRQ				0x56
+#define GPP_H15_IRQ				0x57
+#define GPP_H16_IRQ				0x58
+#define GPP_H17_IRQ				0x59
+#define GPP_H18_IRQ				0x5a
+#define GPP_H19_IRQ				0x5b
+#define GPP_H20_IRQ				0x5c
+#define GPP_H21_IRQ				0x5d
+#define GPP_H22_IRQ				0x5e
+#define GPP_H23_IRQ				0x5f
+/* Group I */
+#define GPP_I0_IRQ				0x18
+#define GPP_I1_IRQ				0x19
+#define GPP_I2_IRQ				0x1a
+#define GPP_I3_IRQ				0x1b
+#define GPP_I4_IRQ				0x1c
+#define GPP_I5_IRQ				0x1d
+#define GPP_I6_IRQ				0x1e
+#define GPP_I7_IRQ				0x1f
+#define GPP_I8_IRQ				0x20
+#define GPP_I9_IRQ				0x21
+#define GPP_I10_IRQ				0x22
+#define GPP_I11_IRQ				0x23
+#define GPP_I12_IRQ				0x24
+#define GPP_I13_IRQ				0x25
+#define GPP_I14_IRQ				0x26
+#define GPP_I15_IRQ				0x27
+#define GPP_I16_IRQ				0x28
+#define GPP_I17_IRQ				0x29
+#define GPP_I18_IRQ				0x2a
+#define GPP_I19_IRQ				0x2b
+#define GPP_I20_IRQ				0x2c
+#define GPP_I21_IRQ				0x2d
+#define GPP_I22_IRQ				0x2e
+#define GPP_I23_IRQ				0x2f
+/* Group J */
+#define GPP_J0_IRQ				0x30
+#define GPP_J1_IRQ				0x31
+#define GPP_J2_IRQ				0x32
+#define GPP_J3_IRQ				0x33
+#define GPP_J4_IRQ				0x34
+#define GPP_J5_IRQ				0x35
+#define GPP_J6_IRQ				0x36
+#define GPP_J7_IRQ				0x37
+#define GPP_J8_IRQ				0x38
+#define GPP_J9_IRQ				0x39
+#define GPP_J10_IRQ				0x3a
+#define GPP_J11_IRQ				0x3b
+#define GPP_J12_IRQ				0x3c
+#define GPP_J13_IRQ				0x3d
+#define GPP_J14_IRQ				0x3e
+#define GPP_J15_IRQ				0x3f
+#define GPP_J16_IRQ				0x40
+#define GPP_J17_IRQ				0x41
+#define GPP_J18_IRQ				0x42
+#define GPP_J19_IRQ				0x43
+#define GPP_J20_IRQ				0x44
+#define GPP_J21_IRQ				0x45
+#define GPP_J22_IRQ				0x46
+#define GPP_J23_IRQ				0x47
+/* Group K */
+#define GPP_K0_IRQ				0x48
+#define GPP_K1_IRQ				0x49
+#define GPP_K2_IRQ				0x4a
+#define GPP_K3_IRQ				0x4b
+#define GPP_K4_IRQ				0x4c
+#define GPP_K5_IRQ				0x4d
+#define GPP_K6_IRQ				0x4e
+#define GPP_K7_IRQ				0x4f
+#define GPP_K8_IRQ				0x50
+#define GPP_K9_IRQ				0x51
+#define GPP_K10_IRQ				0x52
+#define GPP_K11_IRQ				0x53
+#define GPP_K12_IRQ				0x54
+#define GPP_K13_IRQ				0x55
+#define GPP_K14_IRQ				0x56
+#define GPP_K15_IRQ				0x57
+#define GPP_K16_IRQ				0x58
+#define GPP_K17_IRQ				0x59
+#define GPP_K18_IRQ				0x5a
+#define GPP_K19_IRQ				0x5b
+#define GPP_K20_IRQ				0x5c
+#define GPP_K21_IRQ				0x5d
+#define GPP_K22_IRQ				0x5e
+#define GPP_K23_IRQ				0x5f
+/* Register defines. */
+#define GPIO_MISCCFG				0x10
+#define  GPE_DW_SHIFT				8
+#define  GPE_DW_MASK				0xfff00
+#define HOSTSW_OWN_REG_0			0xc0
+#define GPI_SMI_STS_0				0x180
+#define GPI_SMI_EN_0				0x1A0
+#define PAD_CFG_BASE				0x600
+
+#define GPIORXSTATE_MASK			0x1
+#define GPIORXSTATE_SHIFT			1
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
new file mode 100644
index 0000000000..203632d5bb
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_CNP_H_H_
+#define _SOC_CANNONLAKE_GPIO_SOC_DEFS_CNP_H_H_
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+
+#define GPP_A			0
+#define GPP_B			1
+#define GPP_C			2
+#define GPP_D			3
+#define GPP_G			4
+#define GPP_K			5
+#define GPP_H			6
+#define GPP_E			7
+#define GPP_F			8
+#define GPP_I			9
+#define GPP_J			0xA
+#define GPD			0xC
+#define GPIO_NUM_GROUPS		12
+#define GPIO_MAX_NUM_PER_GROUP	24
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+
+/* Group A */
+#define GPP_A0			0
+#define GPP_A1			1
+#define GPP_A2			2
+#define GPP_A3			3
+#define GPP_A4			4
+#define GPP_A5			5
+#define GPP_A6			6
+#define GPP_A7			7
+#define GPP_A8			8
+#define GPP_A9			9
+#define GPP_A10			10
+#define GPP_A11			11
+#define GPP_A12			12
+#define GPP_A13			13
+#define GPP_A14			14
+#define GPP_A15			15
+#define GPP_A16			16
+#define GPP_A17			17
+#define GPP_A18			18
+#define GPP_A19			19
+#define GPP_A20			20
+#define GPP_A21			21
+#define GPP_A22			22
+#define GPP_A23			23
+
+/* Group B */
+#define GPP_B0			24
+#define GPP_B1			25
+#define GPP_B2			26
+#define GPP_B3			27
+#define GPP_B4			28
+#define GPP_B5			29
+#define GPP_B6			30
+#define GPP_B7			31
+#define GPP_B8			32
+#define GPP_B9			33
+#define GPP_B10			34
+#define GPP_B11			35
+#define GPP_B12			36
+#define GPP_B13			37
+#define GPP_B14			38
+#define GPP_B15			39
+#define GPP_B16			40
+#define GPP_B17			41
+#define GPP_B18			42
+#define GPP_B19			43
+#define GPP_B20			44
+#define GPP_B21			45
+#define GPP_B22			46
+#define GPP_B23			47
+
+#define NUM_GPIO_COM0_PADS	(GPP_B23 - GPP_A0 + 1)
+
+/* Group C */
+#define GPP_C0			48
+#define GPP_C1			49
+#define GPP_C2			50
+#define GPP_C3			51
+#define GPP_C4			52
+#define GPP_C5			53
+#define GPP_C6			54
+#define GPP_C7			55
+#define GPP_C8			56
+#define GPP_C9			57
+#define GPP_C10			58
+#define GPP_C11			59
+#define GPP_C12			60
+#define GPP_C13			61
+#define GPP_C14			62
+#define GPP_C15			63
+#define GPP_C16			64
+#define GPP_C17			65
+#define GPP_C18			66
+#define GPP_C19			67
+#define GPP_C20			68
+#define GPP_C21			69
+#define GPP_C22			70
+#define GPP_C23			71
+
+/* Group D */
+#define GPP_D0			72
+#define GPP_D1			73
+#define GPP_D2			74
+#define GPP_D3			75
+#define GPP_D4			76
+#define GPP_D5			77
+#define GPP_D6			78
+#define GPP_D7			79
+#define GPP_D8			80
+#define GPP_D9			81
+#define GPP_D10			82
+#define GPP_D11			83
+#define GPP_D12			84
+#define GPP_D13			85
+#define GPP_D14			86
+#define GPP_D15			87
+#define GPP_D16			88
+#define GPP_D17			89
+#define GPP_D18			90
+#define GPP_D19			91
+#define GPP_D20			92
+#define GPP_D21			93
+#define GPP_D22			94
+#define GPP_D23			95
+
+/* Group G */
+#define GPP_G0			96
+#define GPP_G1			97
+#define GPP_G2			98
+#define GPP_G3			99
+#define GPP_G4			100
+#define GPP_G5			101
+#define GPP_G6			102
+#define GPP_G7			103
+
+#define NUM_GPIO_COM1_PADS	(GPP_G7 - GPP_C0 + 1)
+
+/* Group K */
+#define GPP_K0			104
+#define GPP_K1			105
+#define GPP_K2			106
+#define GPP_K3			107
+#define GPP_K4			108
+#define GPP_K5			109
+#define GPP_K6			110
+#define GPP_K7			111
+#define GPP_K8			112
+#define GPP_K9			113
+#define GPP_K10			114
+#define GPP_K11			115
+#define GPP_K12			116
+#define GPP_K13			117
+#define GPP_K14			118
+#define GPP_K15			119
+#define GPP_K16			120
+#define GPP_K17			121
+#define GPP_K18			122
+#define GPP_K19			123
+#define GPP_K20			124
+#define GPP_K21			125
+#define GPP_K22			126
+#define GPP_K23			127
+
+/* Group H */
+#define GPP_H0			128
+#define GPP_H1			129
+#define GPP_H2			130
+#define GPP_H3			131
+#define GPP_H4			132
+#define GPP_H5			133
+#define GPP_H6			134
+#define GPP_H7			135
+#define GPP_H8			136
+#define GPP_H9			137
+#define GPP_H10			138
+#define GPP_H11			139
+#define GPP_H12			140
+#define GPP_H13			141
+#define GPP_H14			142
+#define GPP_H15			143
+#define GPP_H16			144
+#define GPP_H17			145
+#define GPP_H18			146
+#define GPP_H19			147
+#define GPP_H20			148
+#define GPP_H21			149
+#define GPP_H22			150
+#define GPP_H23			151
+
+/* Group E */
+#define GPP_E0			152
+#define GPP_E1			153
+#define GPP_E2			154
+#define GPP_E3			155
+#define GPP_E4			156
+#define GPP_E5			157
+#define GPP_E6			158
+#define GPP_E7			159
+#define GPP_E8			160
+#define GPP_E9			161
+#define GPP_E10			162
+#define GPP_E11			163
+#define GPP_E12			164
+
+/* Group F */
+#define GPP_F0			165
+#define GPP_F1			166
+#define GPP_F2			167
+#define GPP_F3			168
+#define GPP_F4			169
+#define GPP_F5			170
+#define GPP_F6			171
+#define GPP_F7			172
+#define GPP_F8			173
+#define GPP_F9			174
+#define GPP_F10			175
+#define GPP_F11			176
+#define GPP_F12			177
+#define GPP_F13			178
+#define GPP_F14			179
+#define GPP_F15			180
+#define GPP_F16			181
+#define GPP_F17			182
+#define GPP_F18			183
+#define GPP_F19			184
+#define GPP_F20			185
+#define GPP_F21			186
+#define GPP_F22			187
+#define GPP_F23			188
+
+#define NUM_GPIO_COM3_PADS	(GPP_F23 - GPP_K0 + 1)
+
+/* Group I */
+#define GPP_I0			189
+#define GPP_I1			190
+#define GPP_I2			191
+#define GPP_I3			192
+#define GPP_I4			193
+#define GPP_I5			194
+#define GPP_I6			195
+#define GPP_I7			196
+#define GPP_I8			197
+#define GPP_I9			198
+#define GPP_I10			199
+#define GPP_I11			200
+#define GPP_I12			201
+#define GPP_I13			202
+#define GPP_I14			203
+
+/* Group J */
+#define GPP_J0			204
+#define GPP_J1			205
+#define GPP_J2			206
+#define GPP_J3			207
+#define GPP_J4			208
+#define GPP_J5			209
+#define GPP_J6			210
+#define GPP_J7			211
+#define GPP_J8			212
+#define GPP_J9			213
+#define GPP_J10			214
+#define GPP_J11			215
+
+#define NUM_GPIO_COM4_PADS	(GPP_J11 - GPP_I0 + 1)
+
+/* Group GPD  */
+#define GPD0			216
+#define GPD1			217
+#define GPD2			218
+#define GPD3			219
+#define GPD4			220
+#define GPD5			221
+#define GPD6			222
+#define GPD7			223
+#define GPD8			224
+#define GPD9			225
+#define GPD10			226
+#define GPD11			227
+
+#define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
+
+#define TOTAL_PADS			(GPD11 + 1)
+#endif
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index 90cd3701b5..992e60deac 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -116,6 +116,20 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#define PMC_GPP_A			0x0
+#define PMC_GPP_B			0x1
+#define PMC_GPP_C			0x2
+#define PMC_GPP_D			0x3
+#define PMC_GPP_E			0x7
+#define PMC_GPP_F			0x8
+#define PMC_GPP_G			0x4
+#define PMC_GPP_H			0x6
+#define PMC_GPP_I			0x9
+#define PMC_GPP_J			0xA
+#define PMC_GPP_K			0x5
+#define PMC_GPD				0xC
+#else
 #define  PMC_GPP_A			0x0
 #define  PMC_GPP_B			0x1
 #define  PMC_GPP_C			0xD
@@ -125,6 +139,7 @@
 #define  PMC_GPP_G			0x2
 #define  PMC_GPP_H			0x6
 #define  PMC_GPD			0xA
+#endif
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 6b3ccb2a0d..3cfa2819c2 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -31,7 +31,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 	m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 	m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
 	m_cfg->SaGv = config->SaGv;
-	if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H))
+	if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H))
 		m_cfg->UserBd = BOARD_TYPE_DESKTOP;
 	else
 		m_cfg->UserBd = BOARD_TYPE_ULT_ULX;