diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-02-13 13:43:35 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 18:11:22 +0000 |
| commit | 0de0254a1fef88a8758e0bdc81a25101cd3c9ccd (patch) | |
| tree | fd22c566434e716c60174650d8349adffeb2ea8a /src/soc/intel/cannonlake | |
| parent | 575a2e589d50018946c6e7511cfc98610ea5bac8 (diff) | |
soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboard
Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1]
moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig,
but in doing so inadvertently disabled HECI1 for Puff-based boards which
previously had HECI1 enabled by default. To correct this, move the Kconfig
selection back into the mainboard Kconfig, and set defaults to match values
prior to refactoring in 805956bce.
Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and
ensure Disable HECI1 option defaults to selected for all except Puff.
Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 94f0b4835d..ea50970e0c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -111,9 +111,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2017_BINDING -config DISABLE_HECI1_AT_PRE_BOOT - default y if MAINBOARD_HAS_CHROMEOS - config MAX_CPUS int default 12 |